8.2.1.2.7 Control Loop Compensation

This section walks through the various steps in obtaining the open-loop transfer function. There are three main blocks of a voltage-mode buck converter that the power supply designer must consider when designing the control system: the power stage, the PWM modulator, and the compensated error amplifier. The control loop architecture of a voltage-mode buck converter is provided in Figure 32.

Figure 32. Voltage-mode Buck Converter Architecture

The power stage consists of the filter inductor (L_F) with DCR (DC resistance R_DCR), output capacitor (C_OUT) with ESR (effective series resistance R_ESR), and load resistance (R_O). The LM21215A incorporates a high-bandwidth error amplifier between the FB and COMP pins to achieve high loop bandwidth. The error amplifier (EA) constantly regulates FB to 0.6 V. The compensation component network around the error amplifier establish system stability. The modulator creates the duty cycle command by comparing the error amplifier output with an internally-generated PWM ramp set at the switching frequency.

There are three transfer functions that are taken into consideration when obtaining the total open-loop transfer function; COMP-to-duty cycle (modulator), duty cycle-to-V_OUT (power stage), and V_OUT-to-COMP (compensator). If ΔV_RAMP is the peak-to-peak ramp voltage (nominally 0.8 V), the COMP-to-duty cycle transfer function is simply the PWM modulator gain given by Equation 10.

Equation 10.

The duty cycle-to-output transfer function includes the filter inductor, output capacitor, and output load resistance. The inductor and capacitor create a pair of complex poles at the LC tank frequency expressed by Equation 11.

Equation 11.

In addition to two complex poles, a left half plane zero is created by the output capacitor ESR located at a frequency described by Equation 12.

Equation 12.

A Bode plot showing the –40dB/decade power stage response is shown in Figure 33

Figure 33. Power Stage Bode Plot

The complex poles created by the filter inductor and output capacitor cause a 180° phase lag. The phase is boosted back up to –90° by the output capacitor ESR zero. The compensator must provide sufficient phase boost to stabilize the loop response. The type-III compensation network shown around the error amplifier in Figure 32 creates two poles, two zeros and a pole at the origin. Placing these poles and zeros at the correct frequencies stabilizes the closed loop response. The compensator transfer function is given by Equation 13.

Equation 13.

where

• K_mid is the mid-band gain, R_C1/R_FB1

The pole located at the origin gives high open-loop gain at DC, translating into improved load regulation accuracy. This pole occurs at a very low frequency due to the finite gain of the error amplifier; however, its location is approximated at DC for the purposes of compensation. The other two poles and two zeros are located accordingly to stabilize the voltage-mode loop depending on the power stage complex poles and their quality factor, Q. Figure 34 illustrates a typical type-III compensator transfer function.

Figure 34. Type-III Compensation Network Bode Plot

As seen in Figure 34, the two compensator zeros located at (f_LC/2, f_LC) provide a phase boost. This mitigates the effect of the phase loss from the output filter. The compensation network also adds two poles to the system. One pole is located at the output capacitor ESR zero (f_ESR) and the other pole is at half the switching frequency (F_SW/2) to roll off the high frequency response.

The dependency of the pole and zero locations on the compensation components is described as follows:

The output capacitance, C_OUT, depends on capacitor chemistry and bias voltage. For multi-layer ceramic capacitors (MLCC), the total capacitance degrades as the DC bias voltage is increased. To accurately calculate and optimize the compensation network, it is advisable to determine the effective capacitance of the output capacitors when biased at the output voltage.

The example given here is the total output capacitance using three MLCC output capacitors biased at 1.2 V, as seen in the typical application schematic of Figure 28. 50% capacitance derating is assumed.

First, choose a resistance for R_FB1, a typical value being 10 kΩ. From this, calculate the resistance of R_C1 using Equation 14 to set the mid-band gain such that the desired crossover frequency is achieved.

Equation 14.

Next, calculate the capacitance of C_C1 by placing a zero at half of the LC double pole frequency (f_LC):

Equation 15.

Now calculate C_C2 to place a pole at half of the switching frequency and R_C2 to place the second zero at the LC double pole frequency:

Equation 16.

Equation 17.

Last, derive capacitance of C_C3 to place a pole at the same frequency as the output capacitor ESR zero:

Equation 18.

An illustration of the total loop response is seen in Figure 35.

Figure 35. Loop Response

It is important to verify the stability either by observing the load transient response or by using a network analyzer. A phase margin between 45° and 70° is usually desired for voltage-mode converter circuits. Excessive phase margin causes slow system response to load transients whereas low phase margin leads to an oscillatory load transient response. If the peak deviation of the load transient response is larger than required, increasing f_crossover and recalculating the compensation components may help but usually at the expense of phase margin.