SNVS593J October   2008  – November 2014 LM25085 , LM25085-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings - LM25085
    3. 6.3 Handling Ratings - LM25085-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Regulation Control Circuit
      2. 7.3.2  On-Time Timer
      3. 7.3.3  Shutdown
      4. 7.3.4  Current Limiting
      5. 7.3.5  Current Limit Off-Time
      6. 7.3.6  VCC Regulator
      7. 7.3.7  PGATE Driver Output
      8. 7.3.8  P-Channel MOSFET Selection
      9. 7.3.9  Soft-Start
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode with VIN <4.5 V
      2. 7.4.2 RT Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  RFB1 and RFB2
        2. 8.2.2.2  RT, PFET
        3. 8.2.2.3  L1
        4. 8.2.2.4  RSEN, RADJ
        5. 8.2.2.5  COUT
        6. 8.2.2.6  R3, C1, C2
        7. 8.2.2.7  Alternate Output Ripple Configurations
          1. 8.2.2.7.1 Reduced Ripple Configuration
          2. 8.2.2.7.2 Lowest Cost Configuration
        8. 8.2.2.8  CIN, CBYP
        9. 8.2.2.9  D1
        10. 8.2.2.10 CVCC
        11. 8.2.2.11 IC Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

5 Pin Configuration and Functions

HVSSOP-PowerPad™
8-Lead DGN0008A
Top View
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VSSOP
8-Lead DGK0008A
Top View
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WSON
8-Lead NGQ0008A
Top View
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Pin Functions

PIN I/O DESCRIPTION
NAME NO.
ADJ 1 I Current Limit Adjust - The current limit threshold is set by an external resistor from VIN to ADJ in conjunction with the external sense resistor or the PFET’s RDS(ON).
RT 2 I On-time control and shutdown - An external resistor from VIN to RT sets the buck switch on-time and switching frequency. Grounding this pin shuts down the controller.
FB 3 I Voltage Feedback from the regulated output - Input to the regulation and over-voltage comparators. The regulation level is 1.25V.
GND 4 - Circuit Ground - Ground reference for all internal circuitry.
ISEN 5 I Current sense input for current limit detection. Connect to the PFET drain when using RDS(ON) current sense. Connect to the PFET source and the sense resistor when using a current sense resistor.
PGATE 6 O Gate Driver Output - Connect to the gate of the external PFET.
VCC 7 O Output of the gate driver bias regulator - Output of the negative voltage regulator (relative to VIN) that biases the PFET gate driver. A low ESR capacitor is required from VIN to VCC, located as close as possible to the pins.
VIN 8 I Input supply voltage - The operating input range is from 4.5V to 42V. A low ESR bypass capacitor must be located as close as possible to the VIN and GND pins.
EP - Exposed Pad - Exposed pad on the underside of the package (HVSSOP-PowerPAD-8 and WSON only). This pad is to be soldered to the PC board ground plane to aid in heat dissipation.