JAJSAS9F April   2007  – November 2023 LM25116

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Voltage Start-Up Regulator
      2. 6.3.2 Enable
      3. 6.3.3 UVLO
      4. 6.3.4 Oscillator and Sync Capability
      5. 6.3.5 Error Amplifier and PWM Comparator
      6. 6.3.6 Ramp Generator
      7. 6.3.7 Current Limit
      8. 6.3.8 HO Output
      9. 6.3.9 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Soft Start and Diode Emulation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Timing Resistor
        2. 7.2.2.2  Output Inductor
        3. 7.2.2.3  Current Sense Resistor
        4. 7.2.2.4  Ramp Capacitor
        5. 7.2.2.5  Output Capacitors
        6. 7.2.2.6  Input Capacitors
        7. 7.2.2.7  VCC Capacitor
        8. 7.2.2.8  Bootstrap Capacitor
        9. 7.2.2.9  Soft Start Capacitor
        10. 7.2.2.10 Output Voltage Divider
        11. 7.2.2.11 UVLO Divider
        12. 7.2.2.12 MOSFETs
        13. 7.2.2.13 MOSFET Snubber
        14. 7.2.2.14 Error Amplifier Compensation
        15. 7.2.2.15 Comprehensive Equations
          1. 7.2.2.15.1 Current Sense Resistor and Ramp Capacitor
          2. 7.2.2.15.2 Modulator Transfer Function
          3. 7.2.2.15.3 Error Amplifier Transfer Function
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
7.2.2.15.1 Current Sense Resistor and Ramp Capacitor

T = 1 / fSW, gm = 5 µA/V, A = 10 V/V. IOUT is the maximum output current at current limit.

General method for VOUT < 5 V is Equation 35 and Equation 36.

Equation 35. GUID-86315BFF-B3EA-47E2-8F27-9534D8534E50-low.gif
Equation 36. GUID-037FAF85-1A62-4058-80F8-147486EBE4A7-low.gif

General method for 5 V < VOUT < 7.5 V is Equation 37 and Equation 38.

Equation 37. GUID-E0822AA7-7B34-40BC-9B6D-844DC60CAA75-low.gif
Equation 38. GUID-CF45C95D-6BEA-4A27-8C5E-3F1766AD775F-low.gif

Best performance method minimizes the current limit deviation due to changes in line voltage, while maintaining near optimal slope compensation.

Calculate optimal slope current with Equation 39, IOS = (VOUT / 3) × 10 µA/V. For example, at VOUT = 7.5 V,
IOS = 25 µA.

Equation 39. GUID-45B0BADA-A39A-4AB0-9FEF-222A182FBE61-low.gif

Calculate VRAMP at the nominal input voltage with Equation 40.

Equation 40. GUID-6B234019-B6F3-4F4C-9663-17DEB785E702-low.gif

For VOUT > 7.5 V, install a resistor from the RAMP pin to VCC and calculate with Equation 41.

Equation 41. GUID-7AEF3A93-79D7-4FA4-9C5E-6F4337DF39BE-low.gif
GUID-65A361D5-C74B-4A6B-931C-745837F35172-low.gifFigure 7-6 RRAMP to VCC for VOUT > 7.5 V

For VOUT < 7.5 V, a negative VCC is required. This can be made with a simple charge pump from the LO gate output. Install a resistor from the RAMP pin to the negative VCC and calculate with Equation 42.

Equation 42. GUID-64AF64FA-5889-4DFF-A1B5-5558CCE129E8-low.gif
GUID-A24BBEDE-C733-469F-81A2-AB3E48548C1B-low.gifFigure 7-7 RRAMP to –VCC for VOUT < 7.5 V

If a large variation is expected in VCC, say for VIN < 11 V, a Zener regulator may be added to supply a constant voltage for RRAMP.