JAJSAS9F April   2007  – November 2023 LM25116

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Voltage Start-Up Regulator
      2. 6.3.2 Enable
      3. 6.3.3 UVLO
      4. 6.3.4 Oscillator and Sync Capability
      5. 6.3.5 Error Amplifier and PWM Comparator
      6. 6.3.6 Ramp Generator
      7. 6.3.7 Current Limit
      8. 6.3.8 HO Output
      9. 6.3.9 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Soft Start and Diode Emulation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Timing Resistor
        2. 7.2.2.2  Output Inductor
        3. 7.2.2.3  Current Sense Resistor
        4. 7.2.2.4  Ramp Capacitor
        5. 7.2.2.5  Output Capacitors
        6. 7.2.2.6  Input Capacitors
        7. 7.2.2.7  VCC Capacitor
        8. 7.2.2.8  Bootstrap Capacitor
        9. 7.2.2.9  Soft Start Capacitor
        10. 7.2.2.10 Output Voltage Divider
        11. 7.2.2.11 UVLO Divider
        12. 7.2.2.12 MOSFETs
        13. 7.2.2.13 MOSFET Snubber
        14. 7.2.2.14 Error Amplifier Compensation
        15. 7.2.2.15 Comprehensive Equations
          1. 7.2.2.15.1 Current Sense Resistor and Ramp Capacitor
          2. 7.2.2.15.2 Modulator Transfer Function
          3. 7.2.2.15.3 Error Amplifier Transfer Function
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2.11 UVLO Divider

A voltage divider and filter can be connected to the UVLO pin to set a minimum operating voltage VIN(MIN) for the regulator. If this feature is required, the following procedure is used to determine appropriate resistor values for RUV2, RUV1 and CFT.

  1. RUV2 must be large enough such that in the event of a current limit, the internal UVLO switch can pull UVLO < 200 mV. This can be ensured if: RUV2 > 500 × VIN(MAX), where VIN(MAX) is the maximum input voltage and RUV2 is in ohms.
  2. With an appropriate value for RUV2, RUV1 can be selected using Equation 25.
    Equation 25. GUID-60ADFFBF-D176-476F-B4F9-3CAA1959CB3B-low.gif

    where

    • VIN(MIN) is the desired shutdown voltage
  3. Capacitor CFT provides filtering for the divider and determines the off-time of the hiccup duty cycle during current limit. When CFT is used in conjunction with the voltage divider, a diode across the top resistor must be used to discharge CFT in the event of an input undervoltage condition in Equation 26.
    Equation 26. GUID-DF28A866-B022-4069-B606-17BEC0760973-low.gif

If undervoltage shutdown is not required, RUV1 and RUV2 can be eliminated and the off-time becomes Equation 27.

Equation 27. GUID-77850B02-0B5E-465D-B48E-B9B26A8F29C4-low.gif

The voltage at the UVLO pin must never exceed 16 V when using an external setpoint divider. It may be necessary to clamp the UVLO pin at high input voltages. For the design example, RUV2 = 102 kΩ and
RUV1 = 21 kΩ for a shutdown voltage of 6.6 V. If sustained short-circuit protection is required, CFT ≥ 1 µF limits the short-circuit power dissipation. D2 may be installed when using CFT with RUV1 and RUV2.