Selection of the power MOSFETs is governed by the same tradeoffs as switching frequency. Breaking down the losses in the high-side and low-side MOSFETs is one way to determine relative efficiencies between different devices. When using discrete 8-pin SO MOSFETs, the LM25116 is most efficient for output currents of 2 A to
10 A. Losses in the power MOSFETs can be broken down into conduction loss, gate charging loss, and switching loss. Conduction, or I²R loss P_DC, is approximately Equation 28 and Equation 29.

where

• D is the duty cycle

The factor 1.3 accounts for the increase in MOSFET on-resistance due to heating. Alternatively, the factor of 1.3 can be ignored and the on-resistance of the MOSFET can be estimated using the R_DS(ON) versus Temperature curves in the MOSFET datasheet. Gate charging loss, P_GC, results from the current driving the gate capacitance of the power MOSFETs and is approximated with Equation 30.

Q_g refers to the total gate charge of an individual MOSFET, and ‘n’ is the number of MOSFETs. If different types of MOSFETs are used, the ‘n’ term can be ignored and their gate charges summed to form a cumulative Q_g. Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the LM25116 and not in the MOSFET itself. Further loss in the LM25116 is incurred as the gate driving current is supplied by the internal linear regulator. The gate drive current supplied by the VCC regulator is calculated with Equation 31.

where

• Q_gh + Q_gl represent the gate charge of the HO and LO MOSFETs at VGS = VCC

To ensure start-up, I_GC must be less than the VCC current limit rating of 15 mA minimum when powered by the internal 7.4-V regulator. Failure to observe this rating may result in excessive MOSFET heating and potential damage. The I_GC run current may exceed 15 mA when VCC is powered by VCCX.

Switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition period both current and voltage are present in the channel of the MOSFET. The switching loss can be approximated with Equation 32.

where

• t_R and t_F are the rise and fall times of the MOSFET

Switching loss is calculated for the high-side MOSFET only. Switching loss in the low-side MOSFET is negligible because the body diode of the low-side MOSFET turns on before the MOSFET itself, minimizing the voltage from drain to source before turnon. For this example, the maximum drain-to-source voltage applied to either MOSFET is 42 V. VCC provides the drive voltage at the gate of the MOSFETs. The selected MOSFETs must be able to withstand 42 V plus any ringing from drain to source, and be able to handle at least VCC plus ringing from gate to source. A good choice of MOSFET for the 42-V input design example is the Si7850DP. It has an R_DS(ON) of
20 mΩ, total gate charge of 14 nC, and rise and fall times of 10 ns and 12 ns respectively. In applications where a high step-down ratio is maintained for normal operation, efficiency may be optimized by choosing a high-side MOSFET with lower Q_g, and low-side MOSFET with lower R_DS(ON).

For higher voltage MOSFETs which are not true logic level, it is important to use the UVLO feature. Choose a minimum operating voltage which is high enough for VCC and the bootstrap (HB) supply to fully enhance the MOSFET gates. This prevents operation in the linear region during power-on or power-off which can result in MOSFET failure. Similar consideration must be made when powering VCCX from the output voltage. For the high-side MOSFET, the gate threshold must be considered and careful evaluation made if the gate threshold voltage exceeds the HO driver UVLO.