LM25118-Q1 電圧範囲の広い昇降圧コントローラ
- JAJSDG7 June 2017 LM25118-Q1
  
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LM25118-Q1 電圧範囲の広い昇降圧コントローラ

このリソースの元の言語は英語です。翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

1 特長

車載アプリケーション用にAEC-Q100認定済み
- デバイス温度グレード 1: 動作時周囲温度　　　　　　　–40℃～+125°C
- デバイスHBM ESD分類レベル2
- デバイスCDM ESD分類レベルC6
入力動作電圧範囲: 3V～42V
エミュレーションによるピーク電流モード制御
降圧と昇圧のモード間をスムーズに遷移
スイッチング周波数を最高500kHzにプログラム可能
発振器の同期機能
高電圧バイアス・レギュレータを内蔵
ハイサイドおよびローサイドのゲート・ドライバを内蔵
ソフトスタート時間をプログラム可能
非常に低いシャットダウン電流
イネーブル入力
広帯域幅のエラー・アンプ
1.5%のフィードバック・リファレンス精度
サーマル・シャットダウン
パッケージ: 20ピンのHTSSOP (露出パッド)
WEBENCH® Power Designerにより、LM25118-Q1を使用するカスタム設計を作成

2 アプリケーション

車載インフォテインメント
車載向け始動/停止システム
産業用昇降圧電源

3 概要

LM25118-Q1は広い電圧範囲で動作する昇降圧スイッチング・レギュレータ・コントローラで、最小限の外付け部品で高性能かつコスト効率が高い昇降圧レギュレータを実装するために必要なすべての機能が搭載されています。昇降圧トポロジにより、入力電圧が出力電圧より低くても高くても、出力電圧のレギュレーションが維持されるため、車載用アプリケーションには特に適しています。LM25118は、入力電圧がレギュレートされる出力電圧よりも十分に高いときは降圧レギュレータとして動作し、入力電圧が出力に近付くと、次第に昇降圧モードへ移行します。このデュアル・モード方式により、広い範囲の入力電圧においてレギュレーションが維持され、降圧モードで最適な変換効率を実現し、モード遷移の間も出力にグリッチが発生しません。この使いやすいコントローラには、ハイサイド降圧MOSFETと、ローサイド昇圧MOSFET用のドライバが含まれています。レギュレータの制御方式は、エミュレートされた電流ランプを使用する電流モード制御に基づいています。エミュレートされた電流モード制御を使用することで、パルス幅変調回路のノイズ感受性が低下し、入力電圧の高いアプリケーションに必要な、非常に小さいデューティ・サイクルを高い信頼性で制御できます。さらに、電流制限、サーマル・シャットダウン、イネーブル入力の保護機能が搭載されています。このデバイスは、電力的に強化された20ピンのHTSSOPパッケージで利用可能で、放熱の補助のため露出パッドがダイに取り付けられています。

製品情報⁽¹⁾

型番	パッケージ	本体サイズ(公称)
LM25118-Q1	HTSSOP (20)	6.50mm×4.40mm

提供されているすべてのパッケージについては、巻末の注文情報を参照してください。

概略回路図

LM25118-Q1 typical_application_SNVSAX7.gif

VOUT = 12Vでの効率とVINおよびIOUTとの関係

4 改訂履歴

日付	改訂内容	注
2017年6月	*	初版。車載用デバイスをSNVA726から、スタンドアロンのデータシートへ移動

5 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP With Exposed Pad

Top View

Pin Functions

PIN		TYPE	DESCRIPTION
NO.	NAME	TYPE	DESCRIPTION
1	VIN	P/I	Input supply voltage.
2	UVLO	I	If the UVLO pin is below 1.23 V, the regulator will be in standby mode (VCC regulator running, switching regulator disabled). When the UVLO pin exceeds 1.23 V, the regulator enters the normal operating mode. An external voltage divider can be used to set an undervoltage shutdown threshold. A fixed 5-µA current is sourced out of the UVLO pin. If a current limit condition exists for 256 consecutive switching cycles, an internal switch pulls the UVLO pin to ground and then releases.
3	RT	I	The internal oscillator frequency is set with a single resistor between this pin and the AGND pin. The recommended frequency range is 50 kHz to 500 kHz.
4	EN	I	If the EN pin is below 0.5 V, the regulator will be in a low power state drawing less than 10 µA from VIN. EN must be raised above 3 V for normal operation.
5	RAMP	I	Ramp control signal. An external capacitor connected between this pin and the AGND pin sets the ramp slope used for emulated current mode control.
6	AGND	G	Analog ground.
7	SS	I	Soft-Start. An external capacitor and an internal 10-µA current source set the rise time of the error amp reference. The SS pin is held low when VCC is less than the VCC undervoltage threshold (< 3.7 V), when the UVLO pin is low (< 1.23 V), when EN is low (< 0.5 V) or when thermal shutdown is active.
8	FB	I	Feedback signal from the regulated output. Connect to the inverting input of the internal error amplifier.
9	COMP	O	Output of the internal error amplifier. The loop compensation network should be connected between COMP and the FB pin.
10	VOUT	I	Output voltage monitor for emulated current mode control. Connect this pin directly to the regulated output.
11	SYNC	I	Sync input for switching regulator synchronization to an external clock.
12	CS	I	Current sense input. Connect to the diode side of the current sense resistor.
13	CSG	I	Current sense ground input. Connect to the ground side of the current sense resistor.
14	PGND	G	Power Ground.
15	LO	O	Boost MOSFET gate drive output. Connect to the gate of the external boost MOSFET.
16	VCC	P/I/O	Output of the bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located as close to the controller as possible.
17	VCCX	P/I	Optional input for an externally supplied bias supply. If the voltage at the VCCX pin is greater than 3.9 V, the internal VCC regulator is disabled and the VCC pin is internally connected to VCCX pin supply. If VCCX is not used, connect to AGND.
18	HB	I	High-side gate driver supply used in bootstrap operation. The bootstrap capacitor supplies current to charge the high-side MOSFET gate. This capacitor should be placed as close to the controller as possible and connected between HB and HS.
19	HO	O	Buck MOSFET gate drive output. Connect to the gate of the high side buck MOSFET through a short, low inductance path.
20	HS	I	Buck MOSFET source pin. Connect to the source terminal of the high-side buck MOSFET and the bootstrap capacitor.
—	EP	—	Exposed thermal pad. Solder to the ground plane under the IC to aid in heat dissipation.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
VIN, EN, VOUT to GND	–0.3	45	V
VCC, LO, VCCX, UVLO to GND	–0.3	16	V
HB to HS	–0.3	16	V
HO to HS	–0.3	HB + 0.3	V
HS to GND	–4	45	V
CSG, CS to GND	–0.3	0.3	V
RAMP, SS, COMP, FB, SYNC, RT to GND	–0.3	7	V
Junction temperature	–40	150	°C
Storage temperature, T_stg	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±1000	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
VIN⁽²⁾	3	42	V
VCC, VCCX	4.75	14	V
Junction temperature	–40	+125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM25118-Q1	UNIT
		PWP (HTSSOP)
		20 PINS
R_θJA	Junction-to-ambient thermal resistance	110⁽²⁾	°C/W
		40⁽³⁾
		35⁽⁴⁾
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

(2) JEDEC 2-Layer test board (JESD 51-3)

(3) JEDEC 4-Layer test board (JESD 51-7) with 4 thermal vias under the Exposed Pad

(4) JEDEC 4-Layer test board (JESD 51-7) with 12 thermal vias under the Exposed Pad

6.5 Electrical Characteristics

Unless otherwise specified, the following conditions apply: VIN = 24 V, VCCX = 0 V, EN = 5 V, RT = 29.11 kΩ, no load on LO and HO. Typical values apply for T_J = 25°C; minimum and maximum values apply over the full junction temperature range for operation: −40°C to +125°C.⁽⁴⁾⁽⁴⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VIN SUPPLY
I_BIAS	VIN operating current	VCCX = 0 V		4.5	5.5	mA
I_BIASX	VIN operating current	VCCX = 5 V		1	1.85	mA
I_STDBY	VIN shutdown current	EN = 0 V		1	10	µA
VCC REGULATOR
V_CC(REG)	VCC regulation	VCCX = 0 V	6.8	7	7.2	V
V_CC(REG)	VCC regulation	VCCX = 0 V, VIN = 6 V	5	5.25	5.5	V
	VCC sourcing current limit	VCC = 0	21	35		mA
	VCCX switch threshold	VCCX rising	3.68	3.85	4.02	V
	VCCX switch hysterisis			0.2		V
	VCCX switch RDS(ON)	ICCX = 10 mA		5	12	Ω
	VCCX switch leakage	VCCX = 0 V		0.5	1	µA
	VCCCX pulldown resistance	VCCX = 3 V		70		kΩ
	VCC undervoltage lockout voltage	VCC rising	3.52	3.7	3.86	V
	VCC undervoltage hysterisis			0.21		V
	HB DC bias current	HB-HS = 15 V		205	260	µA
	VC LDO mode turnoff			10		V
EN INPUT
V_EN(OFF)	EN input low threshold	V_EN falling			0.5	V
V_EN(ON)	EN input high threshold	V_EN rising	3			V
	EN input bias current	V_EN = 3 V	–1		1	µA
	EN input bias current	V_EN = 0.5 V	–1		1	µA
	EN input bias current	V_EN = 42 V		50		µA
UVLO THRESHOLDS
UVLO	UVLO standby threshold	UVLO Rising	1.191	1.231	1.271	V
ΔUVLO	UVLO threshold hysteresis			0.105		V
	UVLO pullup current source	UVLO = 0 V		5		µA
	UVLO pulldown R_DS(ON)			100	200	Ω
SOFT START
	SS current source	SS = 0 V	7.5	10.5	13.5	µA
	SS to FB offset	FB = 1.23 V		150		mV
	SS output low voltage	Sinking 100 µA, UVLO = 0 V		7		mV
ERROR AMPLIFIER
V_REF	FB reference voltage	Measured at FB pin, FB = COMP	1.212	1.23	1.248	V
	FB input bias current	FB = 2 V		20	200	nA
	COMP sink/source current		3			mA
A_OL	DC gain			80		dB
f_BW	Unity bain bandwidth			3		MHz
PWM COMPARATORS
t_HO(OFF)	Forced HO off-time		305	400	495	ns
T_ON(MIN)	Minimum HO on-time			70		ns
	COMP to comparator offset			200		mV
OSCILLATOR (RT PIN)
f_SW1	Frequency 1	RT = 29.11 kΩ	178	200	224	kHz
f_SW2	Frequency 2	RT = 9.525 kΩ	450	515	575	kHz
SYNC
	Sync threshold falling			1.3		V
CURRENT LIMIT
V_CS(TH)	Cycle-by-cycle sense voltage threshold (CS-CSG)	RAMP = 0 buck mode	–103	–125	–147	mV
V_CS(THX)	Cycle-by-cycle sense voltage threshold (CS-CSG)	RAMP = 0 buck-boost mode	–218	–255	–300	mV
	CS bias current	CS = 0 V		45	60	µA
	CSG bias current	CSG = 0 V		45	60	µA
	Current limit fault timer			256		cycles
RAMP GENERATOR
I_R2	RAMP current 2	VIN = 12 V, VOUT = 12 V	95	115	135	µA
I_R3	RAMP current 3	VIN = 5 V, VOUT = 12 V	65	80	95	µA
	VOUT bias current	VOUT = 42 V		245		µA
LOW-SIDE (LO) GATE DRIVER
V_OLL	LO low-state output voltage	I_LO = 100 mA		0.14	0.23	V
V_OHL	LO high-state output voltage	I_LO = –100 mA V_OHL = V_CC-V_LO		0.25		V
	LO rise time	C-load = 1 nF, VCC = 8 V		16		ns
	LO fall time	C-load = 1 nF, VCC = 8 V		14		ns
I_OHL	Peak LO source current	V_LO = 0 V, VCC = 8 V		2.2		A
I_OLL	Peak LO sink current	V_LO = VCC = 8 V		2.7		A
HIGH-SIDE (HO) GATE DRIVER
V_OLH	HO low-state output voltage	I_HO = 100 mA		0.135	0.21	V
V_OHH	HO high-state output voltage	I_HO = –100 mA, V_OHH = V_HB-V_OH		0.25		V
	HO rise time	C-load = 1 nF, VCC = 8 V		14		ns
	HO fall time	C-load = 1 nF, VCC = 8 V		12		ns
I_OHH	Peak HO source current	V_HO = 0 V, VCC = 8 V		2.2		A
I_OLH	Peak HO sink current	V_HO = VCC = 8 V		3.5		A
	HB-HS undervoltage lockout			3		V
BUCK-BOOST CHARACTERISTICS⁽³⁾
	Buck-boost mode	Buck duty cycle	69%	75%	80%
THERMAL
T_SD	Thermal shutdown junction temperature			165		°C
ΔT_SD	Thermal shutdown hysterisis			25		°C

(1) Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device should not be operated beyond such conditions. For ensured specifications and conditions, see Electrical Characteristics.

(2) VIN ≥ 5.0 V is required to initially start the controller.

(3) When the duty cycle exceeds 75%, the LM25118-Q1 controller gradually phases into the Buck-Boost mode.

(4) Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only.

6.6 Typical Characteristics

Figure 1. Efficiency vs VIN and IOUT VOUT = 12 V

Figure 3. VCC vs VIN

Figure 5. Error Amplifier Gain/Phase

Figure 7. Oscillator Frequency vs RT

Figure 2. Current Limit Threshold vs VOUT/VIN VOUT = 12 V

Figure 4. VCC vs IVCC

Figure 6. LO and HO Peak Gate Current vs Output Voltage VCC = 8 V