JAJSDG7 June   2017 LM25118-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO
      2. 7.3.2 Oscillator and Sync Capability
      3. 7.3.3 Error Amplifier and PWM Comparator
      4. 7.3.4 Ramp Generator
      5. 7.3.5 Current Limit
      6. 7.3.6 Maximum Duty Cycle
      7. 7.3.7 Soft Start
      8. 7.3.8 HO Output
      9. 7.3.9 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buck Mode Operation: VIN > VOUT
      2. 7.4.2 Buck-Boost Mode Operation: VIN ≊ VOUT
      3. 7.4.3 High Voltage Start-Up Regulator
      4. 7.4.4 Enable
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  R7 = RT
        3. 8.2.2.3  Inductor Selection - L1
        4. 8.2.2.4  R13 = RSENSE
        5. 8.2.2.5  C15 = CRAMP
        6. 8.2.2.6  Inductor Current Limit Calculation
        7. 8.2.2.7  C9 - C12 = Output Capacitors
        8. 8.2.2.8  D1
        9. 8.2.2.9  D4
        10. 8.2.2.10 C1 - C5 = Input Capacitors
        11. 8.2.2.11 C20
        12. 8.2.2.12 C8
        13. 8.2.2.13 C16 = CSS
        14. 8.2.2.14 R8, R9
        15. 8.2.2.15 R1, R3, C21
        16. 8.2.2.16 R2
        17. 8.2.2.17 Snubber
        18. 8.2.2.18 Error Amplifier Configuration
          1. 8.2.2.18.1 R4, C18, C17
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bias Power Dissipation Reduction
    2. 9.2 Thermal Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN, EN, VOUT to GND –0.3 45 V
VCC, LO, VCCX, UVLO to GND –0.3 16 V
HB to HS –0.3 16 V
HO to HS –0.3 HB + 0.3 V
HS to GND –4 45 V
CSG, CS to GND –0.3 0.3 V
RAMP, SS, COMP, FB, SYNC, RT to GND –0.3 7 V
Junction temperature –40 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 ±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN(2) 3 42 V
VCC, VCCX 4.75 14 V
Junction temperature –40 +125 °C

6.4 Thermal Information

THERMAL METRIC(1) LM25118-Q1 UNIT
PWP (HTSSOP)
20 PINS
RθJA Junction-to-ambient thermal resistance 110(2) °C/W
40(3)
35(4)
RθJC(bot) Junction-to-case (bottom) thermal resistance 4 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
(2) JEDEC 2-Layer test board (JESD 51-3)
(3) JEDEC 4-Layer test board (JESD 51-7) with 4 thermal vias under the Exposed Pad
(4) JEDEC 4-Layer test board (JESD 51-7) with 12 thermal vias under the Exposed Pad

6.5 Electrical Characteristics

Unless otherwise specified, the following conditions apply: VIN = 24 V, VCCX = 0 V, EN = 5 V, RT = 29.11 kΩ, no load on LO and HO. Typical values apply for TJ = 25°C; minimum and maximum values apply over the full junction temperature range for operation: −40°C to +125°C.(4)(4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN SUPPLY
IBIAS VIN operating current VCCX = 0 V 4.5 5.5 mA
IBIASX VIN operating current VCCX = 5 V 1 1.85 mA
ISTDBY VIN shutdown current EN = 0 V 1 10 µA
VCC REGULATOR
VCC(REG) VCC regulation VCCX = 0 V 6.8 7 7.2 V
VCC(REG) VCC regulation VCCX = 0 V, VIN = 6 V 5 5.25 5.5 V
VCC sourcing current limit VCC = 0 21 35 mA
VCCX switch threshold VCCX rising 3.68 3.85 4.02 V
VCCX switch hysterisis 0.2 V
VCCX switch RDS(ON) ICCX = 10 mA 5 12 Ω
VCCX switch leakage VCCX = 0 V 0.5 1 µA
VCCCX pulldown resistance VCCX = 3 V 70 kΩ
VCC undervoltage lockout voltage VCC rising 3.52 3.7 3.86 V
VCC undervoltage hysterisis 0.21 V
HB DC bias current HB-HS = 15 V 205 260 µA
VC LDO mode turnoff 10 V
EN INPUT
VEN(OFF) EN input low threshold VEN falling 0.5 V
VEN(ON) EN input high threshold VEN rising 3 V
EN input bias current VEN = 3 V –1 1 µA
EN input bias current VEN = 0.5 V –1 1 µA
EN input bias current VEN = 42 V 50 µA
UVLO THRESHOLDS
UVLO UVLO standby threshold UVLO Rising 1.191 1.231 1.271 V
ΔUVLO UVLO threshold hysteresis 0.105 V
UVLO pullup current source UVLO = 0 V 5 µA
UVLO pulldown RDS(ON) 100 200 Ω
SOFT START
SS current source SS = 0 V 7.5 10.5 13.5 µA
SS to FB offset FB = 1.23 V 150 mV
SS output low voltage Sinking 100 µA, UVLO = 0 V 7 mV
ERROR AMPLIFIER
VREF FB reference voltage Measured at FB pin,
FB = COMP		 1.212 1.23 1.248 V
FB input bias current FB = 2 V 20 200 nA
COMP sink/source current 3 mA
AOL DC gain 80 dB
fBW Unity bain bandwidth 3 MHz
PWM COMPARATORS
tHO(OFF) Forced HO off-time 305 400 495 ns
TON(MIN) Minimum HO on-time 70 ns
COMP to comparator offset 200 mV
OSCILLATOR (RT PIN)
fSW1 Frequency 1 RT = 29.11 kΩ 178 200 224 kHz
fSW2 Frequency 2 RT = 9.525 kΩ 450 515 575 kHz
SYNC
Sync threshold falling 1.3 V
CURRENT LIMIT
VCS(TH) Cycle-by-cycle sense voltage threshold (CS-CSG) RAMP = 0 buck mode –103 –125 –147 mV
VCS(THX) Cycle-by-cycle sense voltage threshold (CS-CSG) RAMP = 0 buck-boost mode –218 –255 –300 mV
CS bias current CS = 0 V 45 60 µA
CSG bias current CSG = 0 V 45 60 µA
Current limit fault timer 256 cycles
RAMP GENERATOR
IR2 RAMP current 2 VIN = 12 V, VOUT = 12 V 95 115 135 µA
IR3 RAMP current 3 VIN = 5 V, VOUT = 12 V 65 80 95 µA
VOUT bias current VOUT = 42 V 245 µA
LOW-SIDE (LO) GATE DRIVER
VOLL LO low-state output voltage ILO = 100 mA 0.14 0.23 V
VOHL LO high-state output voltage ILO = –100 mA
VOHL = VCC-VLO		 0.25 V
LO rise time C-load = 1 nF, VCC = 8 V 16 ns
LO fall time C-load = 1 nF, VCC = 8 V 14 ns
IOHL Peak LO source current VLO = 0 V, VCC = 8 V 2.2 A
IOLL Peak LO sink current VLO = VCC = 8 V 2.7 A
HIGH-SIDE (HO) GATE DRIVER
VOLH HO low-state output voltage IHO = 100 mA 0.135 0.21 V
VOHH HO high-state output voltage IHO = –100 mA,
VOHH = VHB-VOH		 0.25 V
HO rise time C-load = 1 nF, VCC = 8 V 14 ns
HO fall time C-load = 1 nF, VCC = 8 V 12 ns
IOHH Peak HO source current VHO = 0 V, VCC = 8 V 2.2 A
IOLH Peak HO sink current VHO = VCC = 8 V 3.5 A
HB-HS undervoltage lockout 3 V
BUCK-BOOST CHARACTERISTICS(3)
Buck-boost mode Buck duty cycle 69% 75% 80%
THERMAL
TSD Thermal shutdown junction temperature 165 °C
ΔTSD Thermal shutdown hysterisis 25 °C
(1) Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device should not be operated beyond such conditions. For ensured specifications and conditions, see Electrical Characteristics.
(2) VIN ≥ 5.0 V is required to initially start the controller.
(3) When the duty cycle exceeds 75%, the LM25118-Q1 controller gradually phases into the Buck-Boost mode.
(4) Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.

6.6 Typical Characteristics

LM25118-Q1 30165103.gif
Figure 1. Efficiency vs VIN and IOUT VOUT = 12 V
LM25118-Q1 30165105.gif
Figure 3. VCC vs VIN
LM25118-Q1 30165107.gif
Figure 5. Error Amplifier Gain/Phase
LM25118-Q1 30165109.gif
Figure 7. Oscillator Frequency vs RT
LM25118-Q1 30165104.gif
Figure 2. Current Limit Threshold vs VOUT/VIN VOUT = 12 V
LM25118-Q1 30165106.gif
Figure 4. VCC vs IVCC
LM25118-Q1 30165108.gif
Figure 6. LO and HO Peak Gate Current vs Output Voltage VCC = 8 V