JAJSCY9 March   2017 LM25141

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-up Regulator
      2. 7.3.2  VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  Synchronization
      5. 7.3.5  Frequency Dithering (Spread Spectrum)
      6. 7.3.6  Enable
      7. 7.3.7  Power Good
      8. 7.3.8  Output Voltage
        1. 7.3.8.1 Minimum Output Voltage Adjustment
      9. 7.3.9  Current Sense
      10. 7.3.10 DCR Current Sensing
      11. 7.3.11 Error Amplifier and PWM Comparator
      12. 7.3.12 Slope Compensation
      13. 7.3.13 Hiccup Mode Current Limiting
      14. 7.3.14 Standby Mode
      15. 7.3.15 Soft-Start
      16. 7.3.16 Diode Emulation
      17. 7.3.17 High and Low Side Drivers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
      3. 8.2.3 Inductor Calculation
      4. 8.2.4 Current Sense Resistor
      5. 8.2.5 Output Capacitor
      6. 8.2.6 Input Filter
        1. 8.2.6.1 EMI Filter Design
        2. 8.2.6.2 MOSFET Selection
        3. 8.2.6.3 Driver Slew Rate Control
        4. 8.2.6.4 Frequency Dithering
      7. 8.2.7 8.9 Control Loop
        1. 8.2.7.1 Feedback Compensator
      8. 8.2.8 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Procedure
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

Careful PCB layout is critical to achieve low EMI and stable power supply operation. Make the high frequency current loops as small as possible, and follow these guidelines of good layout practices:

  1. Keep the high-current paths short. This is essential for stable, jitter-free operation.
  2. Keep the power traces and load connections short. This is essential for high efficiency. Using 2 oz or thicker copper can enhance full load efficiency.
  3. Minimize current-sensing errors by routing CS and VOUT using a kelvin sensing directly across the current sense resistor (RSENSE).
  4. Route high-speed switching nodes (HB, HO, LO, and SW) away from sensitive analog signals (FB, CS, and VOUT).

10.1.1 Layout Procedure

Place the power components first, with ground terminals adjacent to the low-side FET.

  • Mount the controller IC as close as possible to the high and low-side MOSFETs. Make the grounds and high and low-sided drive gate drive lines as short and wide as possible. Place the series gate drive resistor as close to the MOSFET as possible to minimize gate ringing.
  • Locate the gate drive components (D1 and C12) together and near the controller IC; refer to Figure 38. Be aware that peak gate drive currents can be as high as 4 A. Average current up to 75 mA can flow from the VCC pin to the VCC capacitor through the bootstrap diode to the bootstrap capacitor. Size the traces accordingly.
  • Figure 39 shows the high frequency loops of the synchronous buck converter. The high frequency current flows through Q1 and Q2, through the power ground plane and back to VIN through the ceramic capacitors C6, C7, and C8. This loop must be as small as possible to minimize EMI. Refer to Figure 41 and Figure 42 for the recommended PCB layout.
  • Make the PGND and AGND connections to the LM5141 controller as shown in Figure 40. Create a power grounds directly connected to all high-power components and an analog ground plane for sensitive analog components. The analog ground plane (AGND) and power ground plane (PGND) must be connected at a single point directly under the IC (at the die attach pad or DAP).

10.2 Layout Examples

LM25141 evm_top_side_snvsaj6.png Figure 38. EVM Top Side
LM25141 evm_bottom_layer_high_frequency_current_loop_snvsaj6.png Figure 39. EVM Bottom Layer, High Frequency Current Loop
LM25141 evm_agnd_pgnd_connections_snvsaj6.png Figure 40. AGND and PGND Connections

Figure 41 and Figure 42 show the Top and Bottom layer of the LM5141 EVM.

LM25141 evm_top_layer_snvsaj6.png Figure 41. EVM Top Layer
LM25141 evm_bottom_layer_snvsaj6.png Figure 42. EVM Bottom Layer