JAJSVG8 October   2024 LM251772

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Buck-Boost Control Scheme
        1. 8.3.1.1 Buck Mode
        2. 8.3.1.2 Boost Mode
        3. 8.3.1.3 Buck-Boost Mode
      2. 8.3.2  Power Save Mode
      3. 8.3.3  Reference System
        1. 8.3.3.1 VIO LDO and nRST-PIN
      4. 8.3.4  Supply Voltage Selection – VSMART Switch and Selection Logic
      5. 8.3.5  Enable and Undervoltage Lockout
        1. 8.3.5.1 UVLO
      6. 8.3.6  Internal VCC Regulators
        1. 8.3.6.1 VCC1 Regulator
        2. 8.3.6.2 VCC2 Regulator
      7. 8.3.7  Error Amplifier and Control
        1. 8.3.7.1 Output Voltage Regulation
        2. 8.3.7.2 Output Voltage Feedback
        3. 8.3.7.3 Voltage Regulation Loop
        4. 8.3.7.4 Dynamic Voltage Scaling
      8. 8.3.8  Output Voltage Discharge
      9. 8.3.9  Peak Current Sensor
      10. 8.3.10 Short Circuit - Hiccup Protection
      11. 8.3.11 Current Monitor/Limiter
        1. 8.3.11.1 Overview
        2. 8.3.11.2 Output Current Limitation
        3. 8.3.11.3 Output Current Monitor
      12. 8.3.12 Oscillator Frequency Selection
      13. 8.3.13 Frequency Synchronization
      14. 8.3.14 Output Voltage Tracking
        1. 8.3.14.1 Analog Voltage Tracking
        2. 8.3.14.2 Digital Voltage Tracking
      15. 8.3.15 Slope Compensation
      16. 8.3.16 Configurable Soft Start
      17. 8.3.17 Drive Pin
      18. 8.3.18 Dual Random Spread Spectrum – DRSS
      19. 8.3.19 Gate Driver
      20. 8.3.20 Cable Drop Compensation (CDC)
      21. 8.3.21 CFG-pin and R2D Interface
      22. 8.3.22 Advanced Monitoring Features
        1. 8.3.22.1  Overview
        2. 8.3.22.2  BUSY
        3. 8.3.22.3  OFF
        4. 8.3.22.4  VOUT
        5. 8.3.22.5  IOUT
        6. 8.3.22.6  INPUT
        7. 8.3.22.7  TEMPERATURE
        8. 8.3.22.8  CML
        9. 8.3.22.9  OTHER
        10. 8.3.22.10 ILIM_OP
        11. 8.3.22.11 nFLT/nINT Pin Output
        12. 8.3.22.12 Status Byte
      23. 8.3.23 Protection Features
        1. 8.3.23.1  Thermal Shutdown (TSD)
        2. 8.3.23.2  Over Current Protection
        3. 8.3.23.3  Output Over Voltage Protection 1 (OVP1)
        4. 8.3.23.4  Output Over Voltage Protection 2 (OVP2)
        5. 8.3.23.5  Input Voltage Protection (IVP)
        6. 8.3.23.6  Input Voltage Regulation (IVR)
        7. 8.3.23.7  Power Good
        8. 8.3.23.8  Boot-Strap Under Voltage Protection
        9. 8.3.23.9  Boot-strap Over Voltage Clamp
        10. 8.3.23.10 CRC - CHECK
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overview
      2. 8.4.2 Logic State Description
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
      2. 8.5.2 Clock Stretching
      3. 8.5.3 Data Transfer Formats
      4. 8.5.4 Single READ from a Defined Register Address
      5. 8.5.5 Sequential READ Starting from a Defined Register Address
      6. 8.5.6 Single WRITE to a Defined Register Address
      7. 8.5.7 Sequential WRITE Starting at a Defined Register Address
  10. LM251772 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Custom Design with WEBENCH Tools
        2. 10.2.2.2  Frequency
        3. 10.2.2.3  Feedback Divider
        4. 10.2.2.4  Inductor and Current Sense Resistor Selection
        5. 10.2.2.5  Output Capacitor
        6. 10.2.2.6  Input Capacitor
        7. 10.2.2.7  Slope Compensation
        8. 10.2.2.8  UVLO Divider
        9. 10.2.2.9  Soft-Start Capacitor
        10. 10.2.2.10 MOSFETs QH1 and QL1
        11. 10.2.2.11 MOSFETs QH2 and QL2
        12. 10.2.2.12 Loop Compensation
        13. 10.2.2.13 External Component Selection
      3. 10.2.3 Application Curves
    3. 10.3 Wireless Charging Supply
    4. 10.4 USB-PD Source with Power Path
    5. 10.5 Parallel (Multiphase) Operation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Output Current Limitation

In this configuration the current sense has an internal feedback to the peak current limit of the device. The ILIM circuit regulates the ILIMCOMP voltage to V(ISET), and overrides the voltage loop regulation.

the peak current limit down as long as the differential voltage between ISNSP and ISNSN exceeds the internal offset voltage of the ILIM circuit. The ILIM threshold can be set via the register programming or via the an ISET resistor in the ILIMCOMP pin.

If the current limit threshold is selected by a resistor the regulation overwrites the voltage loop once V(ISET) is increasing to the threshold voltage (typ. 1V). The threshold voltage for ISET can be calculated with:

Equation 15. V ( ISET ) = ( V ( I S N S P ) - V ( I S N S N ) ) g m ( ILIMCOMP ) R ( ILIMCOMP )

Hence the resistor value to select the current limit threshold voltage calculates with:

Equation 16. R ( I S E T ) =   V ( I S E T )   ( V I S N S P   -   V I S N S N )   g m ( I L I M C O M P )

For high frequency noise suppression a capacitor based on the following equation should be placed in parallel to R(ISET)

Equation 17. C ( I S E T ) =   1   π   f ( S W ) R ( I S E T )

If the threshold for the current limit is programmed by the internal DAC the bandwidth of the current limit control loop can be optimized for different loads with a resistor and capacitor network on the ILIMCOMP pin. A simple integrator compensation for resistive loads can be selected according the following equations:

Equation 18. CO2=52πfbwR(LOAD)

Where CO2 is the capacitance after the average current sense resistor R(SNS)

fbw is the bandwidth of the voltage loop compensation (see Voltage Regulation Loop)

Equation 19. C O 1   = C O   -   C O 2  

Where CO is the total output capacitance determined by the voltage loop calculation and the applications voltage ripple requirement.

Where CO1 is the capacitance before the average current sense resistor R(SNS)

Equation 20. fp=12πR(SNS)CO2
Equation 21. f b w i l i m = f p 10 - 0.25
Equation 22. C(ILIMCOMP)=gm(ILIMCOMP)2πfbwilim
LM251772 Simplified Schematic current
                    limit components with resistive load Figure 8-21 Simplified Schematic current limit components with resistive load

For a electronic load (CC-mode CR-mode) a type II compensation network might be necessary to adopt to the internal regulation loop and bandwidth of the used electronic load. Please refer to the Quick Start Calculator Tool for more detailed optimization.

If the current limit threshold is selected by a resistor instead of the internal DAC the regulation overwrites the voltage loop once V(ISET) is increasing to the threshold voltage (typ. 1V). The threshold voltage for ISET can be calculated with:

Equation 23. V ( ISET ) = ( V ( I S N S P ) - V ( I S N S N ) ) g m ( ILIMCOMP ) R ( ISET )

Hence the resistor value to select the current limit threshold voltage calculates with:

Equation 24. R ( I S E T ) =   V ( I S E T )   ( V I S N S P   -   V I S N S N )   g m ( I L I M C O M P )

For high frequency noise suppression a capacitor based on the following equation should be placed in parallel to R(ISET)

Equation 25. C(ISET)= 1 π f(SW)R(ISET)

The read-out register value of the ''ILIM_THRESHOLD" control register is clamped for the lower and for the upper limit of the register range.

  • The reg. readout value is clamped to the lowest clamp current ( e.g. 500mA) if a register value below the value of clamp current been written in before.
  • The reg. readout value is clamped to the highest clamp current if a register value above the highest value of clamp current has been written in before.