JAJSVG8
October 2024
LM251772
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Device Comparison
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
Handling Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Buck-Boost Control Scheme
8.3.1.1
Buck Mode
8.3.1.2
Boost Mode
8.3.1.3
Buck-Boost Mode
8.3.2
Power Save Mode
8.3.3
Reference System
8.3.3.1
VIO LDO and nRST-PIN
8.3.4
Supply Voltage Selection – VSMART Switch and Selection Logic
8.3.5
Enable and Undervoltage Lockout
8.3.5.1
UVLO
8.3.6
Internal VCC Regulators
8.3.6.1
VCC1 Regulator
8.3.6.2
VCC2 Regulator
8.3.7
Error Amplifier and Control
8.3.7.1
Output Voltage Regulation
8.3.7.2
Output Voltage Feedback
8.3.7.3
Voltage Regulation Loop
8.3.7.4
Dynamic Voltage Scaling
8.3.8
Output Voltage Discharge
8.3.9
Peak Current Sensor
8.3.10
Short Circuit - Hiccup Protection
8.3.11
Current Monitor/Limiter
8.3.11.1
Overview
8.3.11.2
Output Current Limitation
8.3.11.3
Output Current Monitor
8.3.12
Oscillator Frequency Selection
8.3.13
Frequency Synchronization
8.3.14
Output Voltage Tracking
8.3.14.1
Analog Voltage Tracking
8.3.14.2
Digital Voltage Tracking
8.3.15
Slope Compensation
8.3.16
Configurable Soft Start
8.3.17
Drive Pin
8.3.18
Dual Random Spread Spectrum – DRSS
8.3.19
Gate Driver
8.3.20
Cable Drop Compensation (CDC)
8.3.21
CFG-pin and R2D Interface
8.3.22
Advanced Monitoring Features
8.3.22.1
Overview
8.3.22.2
BUSY
8.3.22.3
OFF
8.3.22.4
VOUT
8.3.22.5
IOUT
8.3.22.6
INPUT
8.3.22.7
TEMPERATURE
8.3.22.8
CML
8.3.22.9
OTHER
8.3.22.10
ILIM_OP
8.3.22.11
nFLT/nINT Pin Output
8.3.22.12
Status Byte
8.3.23
Protection Features
8.3.23.1
Thermal Shutdown (TSD)
8.3.23.2
Over Current Protection
8.3.23.3
Output Over Voltage Protection 1 (OVP1)
8.3.23.4
Output Over Voltage Protection 2 (OVP2)
8.3.23.5
Input Voltage Protection (IVP)
8.3.23.6
Input Voltage Regulation (IVR)
8.3.23.7
Power Good
8.3.23.8
Boot-Strap Under Voltage Protection
8.3.23.9
Boot-strap Over Voltage Clamp
8.3.23.10
CRC - CHECK
8.4
Device Functional Modes
8.4.1
Overview
8.4.2
Logic State Description
8.5
Programming
8.5.1
I2C Bus Operation
8.5.2
Clock Stretching
8.5.3
Data Transfer Formats
8.5.4
Single READ from a Defined Register Address
8.5.5
Sequential READ Starting from a Defined Register Address
8.5.6
Single WRITE to a Defined Register Address
8.5.7
Sequential WRITE Starting at a Defined Register Address
9
LM251772 Registers
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Custom Design with WEBENCH Tools
10.2.2.2
Frequency
10.2.2.3
Feedback Divider
10.2.2.4
Inductor and Current Sense Resistor Selection
10.2.2.5
Output Capacitor
10.2.2.6
Input Capacitor
10.2.2.7
Slope Compensation
10.2.2.8
UVLO Divider
10.2.2.9
Soft-Start Capacitor
10.2.2.10
MOSFETs QH1 and QL1
10.2.2.11
MOSFETs QH2 and QL2
10.2.2.12
Loop Compensation
10.2.2.13
External Component Selection
10.2.3
Application Curves
10.3
Wireless Charging Supply
10.4
USB-PD Source with Power Path
10.5
Parallel (Multiphase) Operation
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
ドキュメントの更新通知を受け取る方法
11.3
サポート・リソース
11.4
Trademarks
11.5
静電気放電に関する注意事項
11.6
用語集
12
Revision History
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHA|40
MPQF135D
サーマルパッド・メカニカル・データ
RHA|40
QFND660
発注情報
jajsvg8_oa
jajsvg8_pm
8.3
Feature Description