SNVS430I May   2006  – March 2015 LM26001 , LM26001-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - LM26001
    3. 6.3 ESD Ratings - LM26001-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sleep Mode
      2. 7.3.2 FPWM
      3. 7.3.3 Enable
      4. 7.3.4 Soft-Start
      5. 7.3.5 Current Limit
      6. 7.3.6 Frequency Adjustment and Synchronization
      7. 7.3.7 VBIAS
      8. 7.3.8 Low VIN Operation and UVLO
      9. 7.3.9 PGOOD
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting Output Voltage
        2. 8.2.2.2 Inductor
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Bootstrap
        6. 8.2.2.6 Catch Diode
        7. 8.2.2.7 Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations and TSD
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

5 Pin Configuration and Functions

16-Pin
HTSSOP Package
Top View
LM26001 LM26001-Q1 20179402.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 VIN A Power supply input
2 VIN A Power supply input
3 PGOOD O Power Good pin. An open-drain output which goes high when the output voltage is greater than 92% of nominal.
4 EN I Enable is an analog level input pin. When pulled below 0.8 V, the device enters shutdown mode.
5 SS A Soft-start pin. Connect a capacitor from this pin to GND to set the soft-start time.
6 COMP A Compensation pin. Connect to a resistor capacitor pair to compensate the control loop.
7 FB A Feedback pin. Connect to a resistor divider between Vout and GND to set output voltage.
8 GND G Ground
9 FREQ A Frequency adjust pin. Connect a resistor from this pin to GND to set the operating frequency.
10 FPWM I FPWM is a logic level input pin. For normal operation, connect to GND. When pulled high, sleep mode operation is disabled.
11 SYNC I Frequency synchronization pin. Connect to an external clock signal for synchronized operation. SYNC must be pulled low for non-synchronized operation.
12 VBIAS A Connect to an external 3-V or greater supply to bypass the internal regulator for improved efficiency. If not used, VBIAS should be tied to GND.
13 VDD A The output of the internal regulator. Bypass with a minimum 1.0-µF capacitor.
14 BOOT A Bootstrap capacitor pin. Connect a 0.1-µF minimum ceramic capacitor from this pin to SW to generate the gate drive bootstrap voltage.
15 SW A Switch pin. The source of the internal N-channel switch.
16 SW A Switch pin. The source of the internal N-channel switch.
EP EP G Exposed Pad thermal connection. Connect to GND.