JAJSDZ5 October   2017 LM2623-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gated Oscillator Control Scheme
      2. 7.3.2 Cycle-To-Cycle PFM
      3. 7.3.3 Shutdown
      4. 7.3.4 Internal Current Limit and Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Frequency Modulation (PFM)
      2. 7.4.2 Low Voltage Start-Up
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Non-Linear Effect
        2. 8.2.2.2 Choosing the Correct C3 Capacitor
        3. 8.2.2.3 Setting the Output Voltage
        4. 8.2.2.4 VDD Supply
        5. 8.2.2.5 Setting the Switching Frequency
        6. 8.2.2.6 Output Diode Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Boost Output Capacitor Placement
      2. 10.1.2 Schottky Diode Placement
      3. 10.1.3 Boost Input / VDD Capacitor Placement
    2. 10.2 Layout Example
    3. 10.3 WSON Package Devices
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1.1 Boost Output Capacitor Placement

Because the output capacitor is in the path of the inductor current discharge path, it experiences a high-current step from 0 A to the peak inductor current each time the switch turns off, and the Schottky diode turns on. Any inductance along this series path from the diodes cathode, through COUT, and back into the LM2623-Q1 GND pin contributes to voltage spikes at SW. These spikes can potentially overvoltage the SW and BOOST pins, or feed through to GND. To avoid this, COUT+ must be connected as close as possible to the cathode of the Schottky diode, and COUT− must be connected as close as possible to the LM2623-Q1 GND bumps. The best placement for COUT is on the same layer as the LM2623-Q1 to avoid any vias that can add excessive series inductance.