JAJSAX1N January   2008  – June 2017 LM26480

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions: Bucks
    4. 7.4  Thermal Information
    5. 7.5  General Electrical Characteristics
    6. 7.6  Low Dropout Regulators, LDO1 and LDO2
    7. 7.7  Buck Converters SW1, SW2
    8. 7.8  I/O Electrical Characteristics
    9. 7.9  Power On Reset Threshold/Function (POR)
    10. 7.10 Typical Characteristics — LDO
    11. 7.11 Typical Characteristics — Buck 2.8 V to 5.5 V
    12. 7.12 Typical Characteristics — Bucks 1 and 2
    13. 7.13 Typical Characteristics — Buck 3.6 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DC-DC Converters
        1. 8.3.1.1 Linear Low Dropout Regulators (LDOs)
          1. 8.3.1.1.1 No-Load Stability
        2. 8.3.1.2 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters
          1. 8.3.1.2.1  Functional Description
          2. 8.3.1.2.2  Circuit Operation Description
          3. 8.3.1.2.3  Sync Function
          4. 8.3.1.2.4  PWM Operation
          5. 8.3.1.2.5  Internal Synchronous Rectification
          6. 8.3.1.2.6  Current Limiting
          7. 8.3.1.2.7  PFM Operation
          8. 8.3.1.2.8  SW1, SW2 Control
          9. 8.3.1.2.9  Shutdown Mode
          10. 8.3.1.2.10 Soft Start
          11. 8.3.1.2.11 Low Dropout Operation
          12. 8.3.1.2.12 Flexible Power-On Reset (Power Good with Delay)
          13. 8.3.1.2.13 Undervoltage Lockout
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 External Component Selection
      2. 9.1.2 Feedback Resistors for LDOs
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 High VIN- High Load Operation
        2. 9.2.1.2 Junction Temperature
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductors and Capacitors for SW1 AND SW2
          1. 9.2.2.1.1 Inductor Selection for SW1 and SW2
          2. 9.2.2.1.2 Suggested Inductors and Their Suppliers
        2. 9.2.2.2 Output Capacitor Selection for SW1 and SW2
        3. 9.2.2.3 Input Capacitor Selection for SW1 and SW2
        4. 9.2.2.4 LDO Capacitor Selection
          1. 9.2.2.4.1 Input Capacitor
          2. 9.2.2.4.2 Output Capacitor
          3. 9.2.2.4.3 Capacitor Characteristics
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Device Options

Table 1. Default Options

ORDER SUFFIX SPEC OSCILLATOR FREQUENCY BUCK MODES nPOR DELAY UVLO SYNC AECQ
SQ-AA NOPB 2 MHz Auto-Mode 60 ms Enabled Disabled No

Table 2. Power Block Operation

POWER BLOCK INPUT(1) ENABLED DISABLED NOTE
VINLDO12 VIN+ VIN+ Always powered
AVDD VIN+ VIN+ Always powered
VIN1 VIN+ VIN+ or 0V
VIN2 VIN+ VIN+ or 0V
VINLDO1 ≤ VIN+ ≤ VIN+ If enabled, minimum VIN is 1.74 V
VINLDO2 ≤ VIN+ ≤ VIN+ If enabled, minimum VIN is 1.74 V
(1) VIN+ is the largest potential voltage on the device.