10.1.1 Compact Layout

The performance of any switching converter depends as much upon the layout of the PCB as the component selection. The following guidelines help the user design a circuit with maximum rejection of outside EMI and minimum generation of unwanted EMI.

Parasitic inductance can be reduced by keeping the power path components close together and keeping the area of the loops small, on which high currents travel. Short, thick traces or copper pours (shapes) are best. In particular, the switch node (where L1, D1, and the SW pin connect) must be just large enough to connect all three components without excessive heating from the current it carries. The LM2734x and LM2734x-Q1 operate in two distinct cycles (see Figure 27) whose high current paths are shown in Figure 58.

Figure 58. Buck Converter Current Loops

The dark grey, inner loop represents the high current path during the MOSFET on-time. The light grey, outer loop represents the high current path during the off-time.

10.1.2 Ground Plane and Shape Routing

The diagram of Figure 58 is also useful for analyzing the flow of continuous current versus the flow of pulsating currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in routing must be given to the pulsating current paths, as these are the portions of the circuit most likely to emit EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just like any other circuit path. The path between the input source and the input capacitor and the path between the catch diode and the load are examples of continuous current paths. In contrast, the path between the catch diode and the input capacitor carries a large pulsating current. This path must be routed with a short, thick shape, preferably on the component side of the PCB. Multiple vias in parallel must be used right at the pad of the input capacitor to connect the component side shapes to the ground plane. A second pulsating current loop that is often ignored is the gate drive loop formed by the SW and BOOST pins and boost capacitor C_BOOST. To minimize this loop and the EMI it generates, keep C_BOOST close to the SW and BOOST pins.

10.1.3 FB Loop

The FB pin is a high-impedance input, and the loop created by R2, the FB pin and ground must be made as small as possible to maximize noise rejection. R2 must therefore be placed as close as possible to the FB and GND pins of the IC.

10.1.4 PCB Summary

1. Minimize the parasitic inductance by keeping the power path components close together and keeping the area of the high-current loops small.
2. The most important consideration when completing the layout is the close coupling of the GND connections of the C_IN capacitor and the catch diode D1. These ground connections must be immediately adjacent, with multiple vias in parallel at the pad of the input capacitor connected to GND. Place C_IN and D1 as close to the IC as possible.
3. Next in importance is the location of the GND connection of the C_OUT capacitor, which must be near the GND connections of C_IN and D1.
4. There must be a continuous ground plane on the copper layer directly beneath the converter. This reduces parasitic inductance and EMI.
5. The FB pin is a high impedance node and care must be taken to make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors must be placed as close as possible to the IC, with the GND of R2 placed as close as possible to the GND of the IC. The V_OUT trace to R1 must be routed away from the inductor and any other traces that are switching.
6. High AC currents flow through the V_IN, SW and V_OUT traces, so they must be as short and wide as possible. However, making the traces wide increases radiated noise, so the layout designer must make this trade-off. Radiated noise can be decreased by choosing a shielded inductor.

The remaining components must also be placed as close as possible to the IC. See AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines (SNVA054) for further considerations and the LM27342 demo board as an example of a four-layer layout.