JAJSAQ9F November 2008 – September 2016 LM27341 , LM27341-Q1 , LM27342 , LM27342-Q1
PRODUCTION DATA.
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1, 2 | SW | O | Output switch. Connects to the inductor, catch diode, and bootstrap capacitor. |
3 | BOOST | I | Boost voltage that drives the internal NMOS control switch. A bootstrap capacitor is connected between the BOOST and SW pins. |
4 | EN | I | Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN + 0.3 V. |
5 | SYNC | I | Frequency synchronization input. Drive this pin with an external clock or pulse train. Ground it to use the internal clock. |
6 | FB | I | Feedback pin. Connect FB to the external resistor divider to set output voltage. |
7 | GND | G | Signal and power ground pin. Place the bottom resistor of the feedback network as close as possible to this pin for accurate regulation. |
8 | AVIN | I | Supply voltage for the control circuitry. |
9, 10 | PVIN | I | Supply voltage for output power stage. Connect a bypass capacitor to this pin. |
DAP | DAP | G | Signal or power ground and thermal connection. Tie this directly to GND (pin 7). See Application Information regarding optimum thermal layout. |