JAJSA67I April   2004  – February 2019 LM2743

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Start Up and Soft-Start
      2. 8.3.2  Normal Operation
      3. 8.3.3  Tracking a Voltage Level
      4. 8.3.4  Tracking Voltage Slew Rate
      5. 8.3.5  Sequencing
      6. 8.3.6  SD Pin Impedance
      7. 8.3.7  MOSFET Gate Drivers
      8. 8.3.8  Power Good Signal
      9. 8.3.9  UVLO
      10. 8.3.10 Current Limit
      11. 8.3.11 Foldback Current Limit
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Synchronous Buck Converter Typical Application using LM2743
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Duty Cycle Calculation
          3. 9.2.1.2.3 Input Capacitor
          4. 9.2.1.2.4 Output Inductor
          5. 9.2.1.2.5 Output Capacitor
          6. 9.2.1.2.6 MOSFETs
          7. 9.2.1.2.7 Support Components
          8. 9.2.1.2.8 Control Loop Compensation
          9. 9.2.1.2.9 Efficiency Calculations
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Example Circuit 1
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Bill of Materials
      3. 9.2.3 Example Circuit 2
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Bill of Materials
      4. 9.2.4 Example Circuit 3
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Bill of Materials
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.1.2.6 MOSFETs

Selection of the power MOSFETs is governed by a tradeoff between cost, size, and efficiency. One method is to determine the maximum cost that can be endured, and then select the most efficient device that fits that price. Breaking down the losses in the high-side and low-side MOSFETs and then creating spreadsheets is one way to determine relative efficiencies between different MOSFETs. Good correlation between the prediction and the bench result is not specified, however. Single-channel buck regulators that use a controller IC and discrete MOSFETs tend to be most efficient for output currents of 2A to 10A.

Losses in the high-side MOSFET can be broken down into conduction loss, gate charging loss, and switching loss. Conduction loss, or I2R loss, is approximately:

Equation 26. PC = D ((IO)2 x RDSON-HI x 1.3) (High-Side MOSFET)
Equation 27. PC = (1 - D) x ((IO)2 x RDSON-LO x 1.3) (Low-Side MOSFET)

 

In the above equations, the factor 1.3 accounts for the increase in MOSFET RDSON due to heating. Alternatively, the 1.3 can be ignored and the RDSON of the MOSFET estimated using the RDSON Vs. Temperature curves in the MOSFET datasheets.

Gate charging loss results from the current driving the gate capacitance of the power MOSFETs, and is approximated as:

Equation 28. PGC = n x (VDD) x QG x fSW

 

where ‘n’ is the number of MOSFETs (if multiple devices have been placed in parallel), VDD is the driving voltage (see MOSFET Gate Drivers section) and QGS is the gate charge of the MOSFET. If different types of MOSFETs are used, the n term can be ignored and their gate charges simply summed to form a cumulative QG. Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the LM2743, and not in the MOSFET itself.

Switching loss occurs during the brief transition period as the high-side MOSFET turns on and off, during which both current and voltage are present in the channel of the MOSFET. It can be approximated as:

Equation 29. PSW = 0.5 x VIN x IO x (tr + tf) x fSW

 

where tR and tF are the rise and fall times of the MOSFET. Switching loss occurs in the high-side MOSFET only.

For this example, the maximum drain-to-source voltage applied to either MOSFET is 3.6V. The maximum drive voltage at the gate of the high-side MOSFET is 3.1V, and the maximum drive voltage for the low-side MOSFET is 3.3V. Due to the low drive voltages in this example, a MOSFET that turns on fully with 3.1V of gate drive is needed. For designs of 5A and under, dual MOSFETs in SOIC-8 package provide a good trade-off between size, cost, and efficiency.