JAJSAY1E March   2008  – October 2017 LM2854

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Switching Frequency
      2. 7.3.2  Enable
      3. 7.3.3  Soft-Start
      4. 7.3.4  Tracking
      5. 7.3.5  Pre-Biased Start-up Capability
      6. 7.3.6  Feedback Voltage Accuracy
      7. 7.3.7  Positive Current Limit
      8. 7.3.8  Negative Current Limit
      9. 7.3.9  Overtemperature Protection
      10. 7.3.10 Loop Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Soft-Start and Track Mode
      3. 7.4.3 Normal Operating Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Filter Capacitor
        2. 8.2.2.2 AVIN Filtering Components
        3. 8.2.2.3 Soft-Start Capacitor
        4. 8.2.2.4 Tracking - Equal Soft-Start Time
        5. 8.2.2.5 Tracking - Equal Slew Rates
        6. 8.2.2.6 Enable and UVLO
        7. 8.2.2.7 Output Voltage Setting
        8. 8.2.2.8 Compensation Component Selection
        9. 8.2.2.9 Filter Inductor and Output Capacitor Selection
      3. 8.2.3 Application Curves
      4. 8.2.4 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

PWP Package
16-Pin HTSSOP
Top View
LM2854 30052802.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
NC 1, 8, 9 — Reserved for factory use, this pin should be connected to GND to ensure proper operation.
PGND 2, 3, 4 — Power ground pins for the internal power switches. These pins should be connected together locally at the device and tied to the PC board ground plane.
PVIN 5, 6, 7 — Input voltage to the power switches inside the device. These pins should be connected together at the device. A low ESR input capacitance should be located as close as possible to these pins.
AVIN 10 — Analog input voltage supply that generates the internal bias. The UVLO circuit derives its input from this pin also. Thus, if the voltage on AVIN falls below the UVLO threshold, both internal FETs are turned off. TI recommends connecting PVIN to AVIN through a low pass RC filter to minimize the influence of input rail ripple and noise on the analog control circuitry. The series resistor should be 1 Ω and the bypass capacitor should be a X7R ceramic type 0.1 µF to 1 µF.
EN 11 I Active high enable input for the device. Typically, turnon threshold is 1.23 V with 0.15-V hysteresis. An external resistor divider from PVIN can be used to effectively increase the UVLO turnon threshold. If not used, the EN pin should be connected to PVIN.
SW 12, 13 O Switch node pins. This is the PWM output of the internal MOSFET power switches. These pins should be tied together locally and connected to the filter inductor.
SS 14 I/O Soft-start control pin. An internal 2-µA current source charges an external capacitor connected between this pin and AGND to set the output voltage ramp rate during start-up. This pin can also be used to configure the tracking feature.
AGND 15 — Quiet analog ground for the internal bias circuitry.
FB 16 I Feedback pin is connected to the inverting input of the voltage loop error amplifier. An 0.8-V bandgap reference is connected to the noninverting input of the error amplifier.
Exposed Pad — Exposed metal pad on the underside of the package with a weak electrical connection to PGND. TI recommends connecting this pad to the PC board ground plane in order to improve thermal dissipation.