JAJSDE2 June   2017 LM317HV-MIL

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Load Regulation
      2. 7.3.2 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 External Capacitors
      2. 7.4.2 Protection Diodes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1  1.25-V to 45-V High Voltage Adjustable Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2  Digitally Selected Outputs
      3. 8.2.3  Logic Regulator (5-V) With Electronic Shutdown
      4. 8.2.4  Slow Turnon 15-V Regulator
      5. 8.2.5  Adjustable Regulator With Improved Ripple Rejection
      6. 8.2.6  High Stability 10-V Regulator
      7. 8.2.7  High Current Adjustable Regulator
      8. 8.2.8  Emitter Follower Current Amplifier
      9. 8.2.9  1-A Current Regulator
      10. 8.2.10 Common Emitter Amplifier
      11. 8.2.11 Low-Cost, 3-A Switching Regulator
      12. 8.2.12 Adjustable Multiple On-Card Regulators With Single Control
      13. 8.2.13 AC Voltage Regulator
      14. 8.2.14 12-V Battery Charger
      15. 8.2.15 Adjustable 4-A Regulator
      16. 8.2.16 Current Limited 6-V Charger
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 関連リンク
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

Some layout guidelines should be followed to ensure proper regulation of the output voltage with minimum noise. Traces carrying the load current should be wide to reduce the amount of parasitic trace inductance and the feedback loop from V2 to ADJ should be kept as short as possible. To improve PSRR, a bypass capacitor can be placed at the ADJ pin and should be located as close as possible to the IC. In cases when VIN shorts to ground, an external diode should be placed from VOUT to VIN to divert the surge current from the output capacitor and protect the IC. Similarly, in cases when a large bypass capacitor is placed at the ADJ pin and VOUT shorts to ground, an external diode should be placed from ADJ to VOUT to provide a path for the bypass capacitor to discharge. These diodes should be placed close to the corresponding IC pins to increase their effectiveness.

10.2 Layout Example

LM317HV-MIL LM317-TO220-layoutexample.png Figure 33. Layout Example (TO-220 Package)