JAJSHR8G July   2008  – July 2019 LM3421 , LM3423

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的な昇圧アプリケーション
  4. 4 改訂履歴
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Current Regulators
      2. 8.3.2  Predictive Off-Time (PRO) Control
      3. 8.3.3  Average LED Current
      4. 8.3.4  Analog Dimming
      5. 8.3.5  Current Sense and Current Limit
      6. 8.3.6  Overcurrent Protection
      7. 8.3.7  Zero Current Shutdown
      8. 8.3.8  Control Loop Compensation
      9. 8.3.9  Start-Up Regulator
      10. 8.3.10 Overvoltage Lockout (OVLO)
      11. 8.3.11 Input Undervoltage Lockout (UVLO)
        1. 8.3.11.1 UVLO Only
        2. 8.3.11.2 PWM Dimming and UVLO
      12. 8.3.12 PWM Dimming
      13. 8.3.13 LM3423 Only: DPOL, FLT, TIMR, and LRDY
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Inductor
      2. 9.1.2 LED Dynamic Resistance
      3. 9.1.3 Output Capacitor
      4. 9.1.4 Input Capacitors
      5. 9.1.5 Main MOSFET / Dimming MOSFET
      6. 9.1.6 Re-Circulating Diode
      7. 9.1.7 Boost Inrush Current
      8. 9.1.8 Switching Frequency
    2. 9.2 Typical Applications
      1. 9.2.1 Basic Topology Schematics
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Operating Point
          2. 9.2.1.2.2  Switching Frequency
          3. 9.2.1.2.3  Average LED Current
          4. 9.2.1.2.4  Inductor Ripple Current
          5. 9.2.1.2.5  LED Ripple Current
          6. 9.2.1.2.6  Peak Current Limit
          7. 9.2.1.2.7  Loop Compensation
          8. 9.2.1.2.8  Input Capacitance
          9. 9.2.1.2.9  N-channel FET
            1. 9.2.1.2.9.1 Boost and Buck-Boost
          10. 9.2.1.2.10 Diode
          11. 9.2.1.2.11 Output OVLO
          12. 9.2.1.2.12 Input UVLO
          13. 9.2.1.2.13 PWM Dimming Method
          14. 9.2.1.2.14 Analog Dimming Method
      2. 9.2.2 LM3421 Buck-Boost Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1  Operating Point
          2. 9.2.2.2.2  Switching Frequency
          3. 9.2.2.2.3  Average LED Current
          4. 9.2.2.2.4  Inductor Ripple Current
          5. 9.2.2.2.5  Output Capacitance
          6. 9.2.2.2.6  Peak Current Limit
          7. 9.2.2.2.7  Loop Compensation
          8. 9.2.2.2.8  Input Capacitance
          9. 9.2.2.2.9  N-channel FET
          10. 9.2.2.2.10 Diode
          11. 9.2.2.2.11 Input UVLO
          12. 9.2.2.2.12 Output OVLO
        3. 9.2.2.3 Application Curve
      3. 9.2.3 LM3421 BOOST Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
      4. 9.2.4 LM3421 Buck-Boost Application
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
      5. 9.2.5 LM3423 Boost Application
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
      6. 9.2.6 LM3421 Buck-Boost Application
        1. 9.2.6.1 Design Requirements
        2. 9.2.6.2 Detailed Design Procedure
      7. 9.2.7 LM3423 Buck Application
        1. 9.2.7.1 Design Requirements
        2. 9.2.7.2 Detailed Design Procedure
      8. 9.2.8 LM3423 Buck-Boost Application
        1. 9.2.8.1 Design Requirements
        2. 9.2.8.2 Detailed Design Procedure
      9. 9.2.9 LM3421 SEPIC Application
        1. 9.2.9.1 Design Procedure
        2. 9.2.9.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 General Recommendations
    2. 10.2 Input Supply Current Limit
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VIN = 14, −40°C ≤ TJ ≤ 125°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
START-UP REGULATOR
VCCREG VCC regulation ICC = 0 mA 6.3 7.35 V
ICC = 0 mA, TA = 25°C 6.9
ICCLIM VCC current limit VCC = 0 V 20 mA
VCC = 0 V, TA = 25°C 25
IQ Quiescent Current VEN = 3 V, Static 3 mA
VEN = 3 V, Static, TA = 25°C 2
ISD Shutdown current VEN = 0 V 1 µA
VEN = 0 V, TA = 25°C 0.1
VCC SUPPLY
VCCUV VCC UVLO Threshold VCC Increasing 4.5 V
VCC Increasing, TA = 25°C 4.17
VCC Decreasing 3.7
VCC Decreasing, TA = 25°C 4.08
VCCHYS VCC UVLO Hysteresis TA = 25°C 0.1 V
ENABLE THRESHOLDS
ENST EN start-up threshold VEN Increasing 2.4 V
VEN Increasing, TA = 25°C 1.75
ENST EN start-up threshold VEN Decreasing 0.8 V
VEN Decreasing, TA = 25°C 1.63
ENSTHYS EN start-up hysteresis TA = 25°C 0.1 V
REN EN pulldown resistance VEN = 1 V 0.245 2.85 MΩ
VEN = 1 V, TA = 25°C 0.82
CSH THRESHOLDS
CSH high fault CSH Increasing, TA = 25°C 1.6 V
CSH low condition on LRDY Pin CSH increasing, TA = 25°C LM3423 1 V
OV THRESHOLDS
OVPCB OVP OVLO threshold OVP Increasing 1.185 1.285 V
OVP Increasing, TA = 25°C 1.24
OVPHYS OVP hysteresis source current OVP Active (high) 20 25 µA
OVP Active (high), TA = 25°C 23
DPOL THRESHOLDS
DPOLTHRSH DPOL logic threshold DPOL Increasing 2 2.6 V
DPOL Increasing, TA = 25°C 2.3
RDPOL DPOL pullup resistance 1200 kΩ
TA = 25°C 500
FAULT TIMER
VFLTTH Fault threshold 1.185 1.29 V
TA = 25°C 1.24
IFLT FAULT pin source current 10 13 µA
TA = 25°C 11.5
ERROR AMPLIFIER
VREF CSH reference voltage w/r/t to AGND 1.21 1.26 V
w/r/t to AGND, TJ = 25°C 1.235
Error amplifier input bias current TJ = 25°C –0.6 0 0.6 µA
COMP sink or source current 22 35 µA
TJ = 25°C 30
Transconductance TJ = 25°C 100 µA/V
Linear input range  (1), TJ = 25°C ±125 mV
Transconductance bandwidth –6dB Unloaded Response (1),
MIN = TJ = 25°C		 0.5 1 MHz
OFF TIMER
tOFF(min) Minimum OFF-time RCT = 1 V through 1 kΩ 75 ns
RCT = 1 V through 1 kΩ, TJ = 25°C 35
RRCT RCT reset pulldown resistance 120 Ω
TJ = 25°C 36
VRCT VIN/25 reference voltage VIN = 14 V 540 585 mV
VIN = 14 V, TJ = 25°C 565
f Continuous conduction switching frequency 2.2 nF > CT > 470 pF, TJ = 25°C (See (2)) Hz
PWM COMPARATOR
COMP-to-PWM offset voltage 700 900 mV
TJ = 25°C 800
CURRENT LIMIT (IS)
ILIM Current limit threshold 215 275 mV
TJ = 25°C 245
Current limit delay-to-output 75 ns
TJ = 25°C 35
tLEB Leading edge blanking (LEB) time 115 325 ns
TJ = 25°C 210
HIGH SIDE TRANSCONDUCTANCE AMPLIFIER
Input bias current TJ = 25°C 11.5 µA
gM Transconductance 20 mA/V
TJ = 25°C 119
Input offset current –1.5 1.5 µA
TJ = 25°C 0
Input offset voltage –7 7 mV
TJ = 25°C 0
gM(BW) Transconductance bandwidth ICSH = 100 µA(1), TJ = 25°C 250 500 kHz
GATE DRIVER (GATE)
RSRC(GATE) GATE sourcing resistance GATE = High 6 Ω
GATE = High, TJ = 25°C 2
RSNK(GATE) GATE sinking resistance GATE = Low 4.5 Ω
GATE = Low, TJ = 25°C 1.3
DIM DRIVER (DIM, DDRV)
nDIMVTH nDIM / UVLO threshold 1.185 1.285 V
TJ = 25°C 1.24
nDIMHYS nDIM hysteresis current 20 25 µA
TJ = 25°C 23
RSRC(DDRV) DDRV sourcing resistance DDRV = High 30 Ω
DDRV = High, TJ = 25°C 13.5
RSNK(DDRV) DDRV sinking resistance DDRV = Low 10 Ω
DDRV = Low, TJ = 25°C 3.5
PULLDOWN N-CHANNEL MOSFETS
RRPD RPD pulldown resistance 300 Ω
TJ = 25°C 145
RFLT FLT pulldown resistance 300 Ω
TJ = 25°C 145
RLRDY LRDY pulldown resistance 300 Ω
TJ = 25°C 135
THERMAL SHUTDOWN
TSD Thermal shutdown threshold(1)  TJ = 25°C 165 °C
THYS Thermal shutdown hysteresis(1)  TJ = 25°C 25 °C
(1) Specified by design. Not production tested.
(2) f = 25/(CT × RT