7.3.1 Overview of Phase Control Dimming

A basic phase controlled TRIAC dimmer circuit is shown in Figure 9.

Figure 9. Basic TRIAC Dimmer

An RC network consisting of R1, R2, and C1 delay the turn on of the TRIAC until the voltage on C1 reaches the trigger voltage of the diac. Increasing the resistance of the potentiometer (wiper moving downward) increases the turn-on delay which decreases the on-time or conduction angle of the TRIAC (θ). This reduces the average power delivered to the load. Voltage waveforms for a simple TRIAC dimmer are shown in Figure 10. Figure 10a shows the full sinusoid of the input voltage. Even when set to full brightness, few dimmers will provide 100% on-time, i.e., the full sinusoid.

Figure 10. Line Voltage and Dimming Waveforms

Figure 10b shows a theoretical waveform from a dimmer. The on-time is often referred to as the conduction angle and may be stated in degrees or radians. The off-time represents the delay caused by the RC circuit feeding the TRIAC. The off-time be referred to as the firing angle and is simply 180° - θ.

Figure 10c shows a waveform from a so-called reverse phase dimmer, sometimes referred to as an electronic dimmer. These typically are more expensive, microcontroller based dimmers that use switching elements other than TRIACs. Note that the conduction starts from the zero-crossing, and terminates some time later. This method of control reduces the noise spike at the transition.

Since the LM3445 has been designed to assess the relative on-time and control the LED current accordingly, most phase-control dimmers, both forward and reverse phase, may be used with success.

7.3.2 Theory of Operation

Refer to Figure 11 which shows the LM3445 along with basic external circuitry.

Figure 11. LM3445 Schematic

7.3.3 Sensing the Rectified TRIAC Waveform

A bridge rectifier, BR1, converts the line (mains) voltage (Figure 12c) into a series of half-sines as shown in Figure 12b. Figure 12a shows a typical voltage waveform after diode D3 (valley fill circuit, or V_BUCK).

Figure 12. Voltage Waveforms After Bridge Rectifier Without TRIAC Dimming

Figure 13c and Figure 13b show typical TRIAC dimmed voltage waveforms before and after the bridge rectifier. Figure 13a shows a typical TRIAC dimmed voltage waveform after diode D3 (valley fill circuit, or V_BUCK).

Figure 13. Voltage Waveforms After Bridge Rectifier With TRIAC Dimming

7.3.4 LM3445 Line Sensing Circuitry

An external series pass regulator (R2, D1, and Q1) translates the rectified line voltage to a level where it can be sensed by the BLDR pin on the LM3445.

Figure 14. LM3445 AC Line Sense Circuitry

D1 is typically a 15-V Zener diode which forces transistor Q1 to stand-off most of the rectified line voltage. Having no capacitance on the source of Q1 allows the voltage on the BLDR pin to rise and fall with the rectified line voltage as the line voltage drops below zener voltage D1 (see Angle Detect).

A diode-capacitor network (D2, C5) is used to maintain the voltage on the VCC pin while the voltage on the BLDR pin goes low. This provides the supply voltage to operate the LM3445.

Resistor R5 is used to bleed charge out of any stray capacitance on the BLDR node and may be used to provide the necessary holding current for the dimmer when operating at light output currents.

7.3.5 TRIAC Holding Current Resistor

In order to emulate an incandescent light bulb (essentially a resistor) with any LED driver, the existing TRIAC will require a small amount of holding current throughout the AC line cycle. An external resistor (R5) needs to be placed on the source of Q1 to GND to perform this function. Most existing TRIAC dimmers only require a few milliamps of current to hold them on. A few less expensive TRIACs sold on the market will require a bit more current. The value of resistor R5 will depend on:

• What type of TRIAC the LM3445 will be used with
• How many light fixtures are running off of the TRIAC

With a single LM3445 circuit on a common TRIAC dimmer, a holding current resistor between 3 kΩ and 5 kΩ will be required. As the number of LM3445 circuits is added to a single dimmer, the holding resistor R5’s resistance can be increased. A few TRIAC dimmers will require a resistor as low as 1 kΩ or lower for a single LM3445 circuit. The trade-off will be performance vs efficiency. As the holding resistor R5 is increased, the overall efficiency per LM3445 will also increase.

7.3.6 Angle Detect

The Angle Detect circuit uses a comparator with a fixed threshold voltage of 7.21 V to monitor the BLDR pin to determine whether the TRIAC is on or off. The output of the comparator drives the ASNS buffer and also controls the Bleeder circuit. A 4 µs delay line on the output is used to filter out noise that could be present on this signal.

The output of the Angle Detect circuit is limited to a 0 V to 4 V swing by the buffer and presented to the ASNS pin. R1 and C3 comprise a low-pass filter with a bandwidth on the order of 1 Hz.

The Angle Detect circuit and its filter produce a DC level which corresponds to the duty cycle (relative on-time) of the TRIAC dimmer. As a result, the LM3445 will work equally well with 50-Hz or 60-Hz line voltages.

7.3.7 Bleeder

While the BLDR pin is below the 7.21-V threshold, the bleeder MOSFET is on to place a small load (230 Ω) on the series pass regulator. This additional load is necessary to complete the circuit through the TRIAC dimmer so that the dimmer delay circuit can operate correctly. Above 7.21 V, the bleeder resistor is removed to increase efficiency.

7.3.8 FLTR1 Pin

The FLTR1 pin has two functions. Normally, it is fed by ASNS through filter components R1 and C3 and drives the dim decoder. However, if the FLTR1 pin is tied above 4.9 V (typical), for example, to VCC, the Ramp Comparator is tri-stated, disabling the dim decoder. See Master/Slave Operation

7.3.9 Dim Decoder

The ramp generator produces a 5.85-kHz saw tooth wave with a minimum of 1 V and a maximum of 3 V. The filtered ASNS signal enters pin FLTR1 where it is compared against the output of the Ramp Generator.

The output of the ramp comparator will have an on-time which is inversely proportional to the average voltage level at pin FLTR1. However, since the FLTR1 signal can vary between 0 V and 4 V (the limits of the ASNS pin), and the Ramp Generator signal only varies between 1 V and 3 V, the output of the ramp comparator will be on continuously for V_FLTR1 < 1 V and off continuously for V_FLTR1 > 3 V. This allows a decoding range from 45° to 135° to provide a 0 to 100% dimming range.

The output of the ramp comparator drives both a common-source N-channel MOSFET through a Schmitt trigger and the DIM pin (see Master/Slave Operation for further functions of the DIM pin). The MOSFET drain is pulled up to 750 mV by a 50-kΩ resistor.

Since the MOSFET inverts the output of the ramp comparator, the drain voltage of the MOSFET is proportional to the duty cycle of the line voltage that comes through the TRIAC dimmer. The amplitude of the ramp generator causes this proportionality to "hard limit" for duty cycles above 75% and below 25%.

The MOSFET drain signal next passes through an RC filter comprised of an internal 370-kΩ resistor, and an external capacitor on pin FLTR2. This forms a second low pass filter to further reduce the ripple in this signal, which is used as a reference by the PWM comparator. This RC filter is generally set to 10 Hz.

The net effect is that the output of the dim decoder is a DC voltage whose amplitude varies from near 0 V to 750 mV as the duty cycle of the dimmer varies from 25% to 75%. This corresponds to conduction angles of 45° to 135°, respectively.

The output voltage of the Dim Decoder directly controls the peak current that will be delivered by Q2 during its on-time. See Buck Converter for details.

As the TRIAC fires beyond 135°, the DIM decoder no longer controls the dimming. At this point the LEDs will dim gradually for one of two reasons:

1. The voltage at V_BUCK decreases and the buck converter runs out of headroom and causes LED current to decrease as V_BUCK decreases.
2. Minimum on-time is reached which fixes the duty-cycle and therefore reduces the voltage at V_BUCK.

The transition from dimming with the DIM decoder to headroom or minimum on-time dimming is seamless. LED currents from full load to as low as 0.5 mA can be easily achieved.

7.3.10 Valley-Fill Circuit

V_BUCK supplies the power which drives the LED string. Diode D3 allows V_BUCK to remain high while V+ cycles on and off. V_BUCK has a relatively small hold capacitor C10 which reduces the voltage ripple when the valley fill capacitors are being charged. However, the network of diodes and capacitors shown between D3 and C10 make up a valley-fill circuit. The valley-fill circuit can be configured with two or three stages. The most common configuration is two stages. Figure 15 illustrates a two and three stage valley-fill circuit.

Figure 15. Two and Three Stage Valley Fill Circuit

The valley-fill circuit allows the buck regulator to draw power throughout a larger portion of the AC line. This allows the capacitance needed at V_BUCK to be lower than if there were no valley-fill circuit, and adds passive power factor correction (PFC) to the application. Besides better power factor correction, a valley-fill circuit allows the buck converter to operate while separate circuitry translates the dimming information. This allows for dimming that isn’t subject to 120Hz flicker that can be perceived by the human eye.

7.3.11 Valley-Fill Operation

When the input line is high, power is derived directly through D3. The term input line is high can be explained as follows. The valley-fill circuit charges capacitors C7 and C9 in series (see Figure 16) when the input line is high.

Figure 16. Two Stage Valley-Fill Circuit When AC Line is High

The peak voltage of a two stage valley-fill capacitor is:

Equation 1.

As the AC line decreases from its peak value every cycle, there will be a point where the voltage magnitude of the AC line is equal to the voltage that each capacitor is charged. At this point diode D3 becomes reversed biased, and the capacitors are placed in parallel to each other (Figure 17), and V_BUCK equals the capacitor voltage.

Figure 17. Two Stage Valley-Fill Circuit When AC Line is Low

A three stage valley-fill circuit performs exactly the same as two-stage valley-fill circuit except now three capacitors are now charged in series, and when the line voltage decreases to:

Equation 2.

Diode D3 is reversed biased and three capacitors are in parallel to each other.

The valley-fill circuit can be optimized for power factor, voltage hold up and overall application size and cost. The LM3445 will operate with a single stage or a three stage valley-fill circuit as well. Resistor R8 functions as a current limiting resistor during start-up, and during the transition from series to parallel connection. Resistors R6 and R7 are 1-MΩ bleeder resistors, and may or may not be necessary for each application.

7.3.12 Buck Converter

The LM3445 is a buck controller that uses a proprietary constant off-time method to maintain constant current through a string of LEDs. While transistor Q2 is on, current ramps up through the inductor and LED string. A resistor R3 senses this current and this voltage is compared to the reference voltage at FLTR2. When this sensed voltage is equal to the reference voltage, transistor Q2 is turned off and diode D10 conducts the current through the inductor and LEDs. Capacitor C12 eliminates most of the ripple current seen in the inductor. Resistor R4, capacitor C11, and transistor Q3 provide a linear current ramp that sets the constant off-time for a given output voltage.

Figure 18. LM3445 Buck Regulation Circuit

7.3.13 Overview of Constant Off-Time Control

A buck converter’s conversion ratio is defined using Equation 3.

Equation 3.

Constant off-time control architecture operates by simply defining the off-time and allowing the on-time, and therefore the switching frequency, to vary as either V_IN or V_O changes. The output voltage is equal to the LED string voltage (V_LED), and should not change significantly for a given application. The input voltage or V_BUCK in this analysis will vary as the input line varies. The length of the on-time is determined by the sensed inductor current through a resistor to a voltage reference at a comparator. During the on-time, denoted by t_ON, MOSFET switch Q2 is on causing the inductor current to increase. During the on-time, current flows from V_BUCK, through the LEDs, through L2, Q2, and finally through R3 to ground. At some point in time, the inductor current reaches a maximum (I_L2-PK) determined by the voltage sensed at R3 and the ISNS pin. This sensed voltage across R3 is compared against the voltage of dim decoder output, FLTR2, at which point Q2 is turned off by the controller.

Figure 19. Inductor Current Waveform in CCM

During the off-period denoted by t_OFF, the current through L2 continues to flow through the LEDs via D10.

7.3.14 Master/Slave Operation

Multiple LM3445s can be configured so that large strings of LEDs can be controlled by a single TRIAC dimmer. By doing so, smooth consistent dimming for multiple LED circuits is achieved.

When the FLTR1 pin is tied above 4.9 V (typical), preferably to VCC, the ramp comparator is tri-stated, disabling the dim decoder. This allows one or more LM3445 devices or PWM LED driver devices (slaves) to be controlled by a single LM3445 (master) by connecting their DIM pins together.

7.3.15 Master/Slave Configuration

TI offers an LM3445 demonstration PCB for customer evaluation through our website. The following description and theory uses reference designators that follow our evaluation PCB. The LM3445 Master/Slave schematics are illustrated below (Figure 20 through Figure 22) for clarity. Each board contains a separate circuit for the Master and Slave function. Both the Master and Slave boards will need to be modified from their original stand alone function so that they can be coupled together. Only the Master LM3445 requires use of the Master/Slave circuit for any number of slaves.

7.3.16 Master Board Modifications

• Remove R10 and replace with a BAS40 diode
• Connect TP18 to TP14 (V_CC)
• Connect TP17 (gate of Q5) to TP15 (gate of Q2)

7.3.17 Slave Board Modifications

• Remove R11 (disconnects BLDR)
• Tie TP14 (FLTR1) to V_CC

7.3.18 Master/Slave Interconnection

• Connect TP19 of Master to TP10 of Slave (Master VCC Control)
• Connect TP6 (DIM pin) of Master to TP6 (DIM pin) of Slave (Master DIM Control)

7.3.19 Master/Slave Theory of Operation

By placing two series diodes on the Master VCC circuit one forces the master VCC UVLO to become the dominant threshold. When Master VCC drops below UVLO, GATE stops switching and the RC timer (>200 µs) rises above the TL431 threshold (2.5 V) which in turn pulls down on the gate of the Slave pass device (Q1).

The valley-fill circuit could consist of one large circuit to power all LM3445 series connected, or each LM3445 circuit could have a separate valley-fill circuit located near the buck converter.

7.3.20 Master/Slave Connection Diagram

Figure 20. Master Slave Configuration

7.3.21 Master/Slave Block Diagrams

Figure 21. Master/Slave Configuration With Separate Valley-Fill Circuits

Figure 22. Master/Slave Configuration With One Valley-Fill Circuit

7.3.22 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature exceeds 165°C. After thermal shutdown occurs, the output switch doesn’t turn on until the junction temperature drops to approximately 145°C.