JAJSG33A September   2018  – August 2021 LM34936

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation
      2. 7.3.2  VCC Regulator and Optional BIAS Input
      3. 7.3.3  Enable/UVLO
      4. 7.3.4  Soft-Start
      5. 7.3.5  Overcurrent Protection
      6. 7.3.6  Average Input/Output Current Limiting
      7. 7.3.7  Operation Above 28-V Input
      8. 7.3.8  CCM Operation
      9. 7.3.9  Frequency and Synchronization (RT/SYNC)
      10. 7.3.10 Frequency Dithering
      11. 7.3.11 Output Overvoltage Protection (OVP)
      12. 7.3.12 Power Good (PGOOD)
      13. 7.3.13 Gm Error Amplifier
      14. 7.3.14 Integrated Gate Drivers
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown, Standby, and Operating Modes
      2. 7.4.2 MODE Pin Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH Tools
        2. 8.2.2.2  Frequency
        3. 8.2.2.3  VOUT
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor
        6. 8.2.2.6  Input Capacitor
        7. 8.2.2.7  Sense Resistor (RSENSE)
        8. 8.2.2.8  Slope Compensation
        9. 8.2.2.9  UVLO
        10. 8.2.2.10 Soft-Start Capacitor
        11. 8.2.2.11 Dither Capacitor
        12. 8.2.2.12 MOSFETs QH1 and QL1
        13. 8.2.2.13 MOSFETs QH2 and QL2
        14. 8.2.2.14 Frequency Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design with WEBENCH Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature range unless otherwise stated. VIN = 24 V unless otherwise stated.(1)
PARAMETERTEST CONDITIONMINTYPMAXUNIT
SUPPLY VOLTAGE (VIN)
IQVIN shutdown currentVEN/UVLO = 0 V2.610µA
VIN operating currentVEN/UVLO = 2 V, VFB = 0.9 V24mA
VCC
VVCC(VIN)Regulation voltageVBIAS = 0 V, VCC open6.957.357.88V
VUV(VCC)VCC Undervoltage lockoutVCC increasing3.113.273.43
Undervoltage hysteresis176mV
IVCCVCC current limitVVCC = 0 V65mA
ROUT(VCC)VCC regulator output impedanceIVCC = 30 mA, VIN = 4 V816Ω
BIAS
VBIAS(SW)BIAS switchover voltageVIN = 24 V7.2588.75V
EN/UVLO
VEN(STBY)Standby thresholdEN/UVLO rising0.550.820.97V
IEN(STBY)Standby source currentVEN/UVLO = 1.1 V123µA
VEN(OP)Operating thresholdEN/UVLO rising1.171.221.29V
ΔIHYS(OP)Operating hysteresis currentVEN/UVLO = 1.5 V2.153.154.25µA
SS
ISSSoft-start pull up currentVSS = 0 V3.7556.35µA
VSS(CL)SS clamp voltageSS open1.21V
VFB - VSSFB to SS offsetVSS = 0 V-18mV
EA (ERROR AMPLIFIER)
VREFFeedback reference voltageFB = COMP0.7880.8000.812V
gmEAError amplifier gm1.31mS
ISINK/ISOURCECOMP sink/source currentVFB=VREF ± 300 mV280µA
ROUTAmplifier output resistance20MΩ
BWUnity gain bandwidth2MHz
IBIAS(FB)Feedback pin input bias currentFB in regulation25nA
FREQUENCY
fSW(1)Switching Frequency 1RT = 40 kΩ175200225kHz
fSW(2)Switching Frequency 2RT = 20 kΩ350390430
DITHER
IDITHERDither source/sink current11µA
VDITHERDither high threshold1.27V
Dither low threshold1.16
SYNC
VSYNCSync input high threshold2.1V
Sync input low threshold1.2
PWSYNCMinimum sync input pulse width50ns
CURRENT LIMIT
VCS(BUCK)Buck current limit threshold (Valley)VIN = VVISNS = 24 V, VVOSNS = 12 V, VSLOPE = 0 V608094mV
VCS(BOOST)Boost current limit threshold (Peak)VIN = VVISNS = 12 V, VVOSNS = 18 V, VSLOPE = 0 V96120140
IBIAS(CS/CSG)CS/CSG pin bias currentVCS = VCSG = 0 V-80µA
IOFFSET(CS/CSG)CSG pin bias currentVCS = VCSG = 0 V19
CONSTANT CURRENT LOOP
VSNSAverage current loop regulation targetVISNS(-) = 24 V, sweep ISNS(+), VSS = 0.8 V435057mV
ISNSISNS(+)/ISNS(–) pin bias currentsVISNS(+) = VISNS(–) = VIN = 24 V3µA
Gmgm of soft-start pull down amplifierVISNS(+)–VISNS(–) = 55 mV, VSS = 0.5 V1mS
SLOPE
ISLOPEBuck adaptive slope currentVIN = VVISNS = 24 V, VVOSNS = 12 V, VSLOPE = 0 V243035µA
Boost adaptive slope currentVIN = VVISNS = 12 V, VVOSNS = 18 V, VSLOPE = 0 V131721
gmSLOPESlope compensation amplifier gm2µS
MODE
IMODESource current out of MODE pin172023µA
VCCM_HICCCM with hiccup threshold1.181.281.38V
VCCMCCM no hiccup threshold2.222.42.6V
PGOOD
VPGDPGOOD trip threshold for falling FBMeasured with respect to VREF–9%
PGOOD trip threshold for rising FBMeasured with respect to VREF10%
Hysteresis2.5%
ILEAK(PGD)PGOOD leakage current100nA
ISINK(PGD)PGOOD sink currentVPGOOD = 0.4 V24.26.5mA
OUTPUT OVP
VOVPOutput overvoltage threshold at FB pinMeasured with respect to VREF10%
Hysteresis2.5%
NMOS DRIVERS
IHDRV1,2Driver peak source currentVBOOT - VSW = 7 V1.8A
Driver peak sink currentVBOOT - VSW = 7 V2.2
ILDRV1,2Driver peak source current1.8
Driver peak sink current2.2
RHDRV1,2Driver pull up resistanceVBOOT - VSW = 7 V1.8Ω
Driver pull down resistanceVBOOT - VSW = 7 V1.1
VUV(BOOT1,2)BOOT1,2 to SW1,2 UVLO thresholdHDRV1,2 shut off3.4V
BOOT1,2 to SW1,2 UVLO hysteresisHDRV1,2 start switching150mV
RLDRV1,2Driver pull up resistance1.7Ω
Driver pull down resistance1.3
tDT1Dead time HDRV1,2 off to LDRV1,2 on45ns
tDT2Dead time LDRV1,2 off to HDRV1,2 on45
THERMAL SHUTDOWN
TSDThermal shutdown temperature165°C
TSD(HYS)Thermal shutdown hysteresis15
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.