JAJSDP5D February   2016  – March 2018 LM36273

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     概略回路図
  3. 3 概要
    1.     バックライト効率、3P7S
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements (Fast Mode)
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Features Description
      1. 7.3.1 Enabling the LM36273
      2. 7.3.2 Backlight
        1. 7.3.2.1 Current Sink Enable
        2. 7.3.2.2 Brightness Mapping
          1. 7.3.2.2.1 Linear Mapping
          2. 7.3.2.2.2 Exponential Mapping
        3. 7.3.2.3 Backlight Brightness Control Modes
          1. 7.3.2.3.1 I2C Brightness Control (PWM Pin Disabled)
          2. 7.3.2.3.2 I2C × PWM Brightness Control (PWM Pin Enabled)
            1. 7.3.2.3.2.1 PWM Ramper
        4. 7.3.2.4 Boost Switching Frequency
          1. 7.3.2.4.1 Minimum Inductor Select
        5. 7.3.2.5 Boost Feedback Gain Select
        6. 7.3.2.6 Auto Switching Frequency
        7. 7.3.2.7 PWM Input
          1. 7.3.2.7.1 PWM Sample Frequency
            1. 7.3.2.7.1.1 PWM Resolution and Input Frequency Range
            2. 7.3.2.7.1.2 PWM Sample Rate and Efficiency
              1. 7.3.2.7.1.2.1 PWM Sample Rate Example
          2. 7.3.2.7.2 PWM Hysteresis
          3. 7.3.2.7.3 PWM Step Response
          4. 7.3.2.7.4 PWM Timeout
          5. 7.3.2.7.5 PWM-to-Digital Code Readback
        8. 7.3.2.8 Regulated Headroom Voltage
        9. 7.3.2.9 Backlight Fault Protection and Faults
          1. 7.3.2.9.1 Backlight Overvoltage Protection (OVP)
          2. 7.3.2.9.2 Backlight Overcurrent Protection (OCP)
      3. 7.3.3 LCM Bias
        1. 7.3.3.1 Display Bias Boost Converter (VVPOS, VVNEG)
        2. 7.3.3.2 Auto Sequence Mode
        3. 7.3.3.3 Wake-up Mode
          1. 7.3.3.3.1 Wake1 Mode
          2. 7.3.3.3.2 Wake2 Mode
        4. 7.3.3.4 Active Discharge
        5. 7.3.3.5 LCM Bias Protection and Faults
          1. 7.3.3.5.1 LCM Overvoltage (OVP) Protection
          2. 7.3.3.5.2 VPOS Short-Circuit Protection
          3. 7.3.3.5.3 VNEG Short-Circuit Protection
      4. 7.3.4 Software Reset
      5. 7.3.5 HWEN Input
      6. 7.3.6 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Serial Bus Interface
        1. 7.5.1.1 Interface Bus Overview
        2. 7.5.1.2 Data Transactions
        3. 7.5.1.3 Acknowledge Cycle
        4. 7.5.1.4 Acknowledge After Every Byte Rule
        5. 7.5.1.5 Addressing Transfer Formats
        6. 7.5.1.6 Register Programming
    6. 7.6 Register Maps
      1. 7.6.1  Revision Register (Address = 0x01)[Reset = 0x01]
        1. Table 11. Revision Register Field Descriptions
      2. 7.6.2  Backlight Configuration1 Register (Address = 0x02)[Reset = 0x28]
        1. Table 12. Backlight Configuration 1 Register Field Descriptions
      3. 7.6.3  Backlight Configuration 2 Register (Address = 0x03)[Reset = 0x8D]
        1. Table 13. Backlight Configuration 2 Register Field Descriptions
      4. 7.6.4  Backlight Brightness LSB Register (Address = 0x04)[Reset = 0x07]
        1. Table 14. Backlight Brightness LSB Register Field Descriptions
      5. 7.6.5  Backlight Brightness MSB Register (Address = 0x05)[Reset = 0xFF]
        1. Table 15. Backlight Brightness MSB Register Field Descriptions
      6. 7.6.6  Backlight Auto-Frequency Low Threshold Register (Address = 0x06)[Reset = 0x00]
        1. Table 16. Backlight Auto-Frequency Low Threshold Field Descriptions
      7. 7.6.7  Backlight Auto-Frequency High Threshold Register (Address = 0x07)[Reset = 0x00]
        1. Table 17. Backlight Auto-Frequency High Threshold Field Descriptions
      8. 7.6.8  Backlight Enable Register (Address = 0x08)[Reset = 0x00]
        1. Table 18. Backlight Enable Register Field Descriptions
      9. 7.6.9  Bias Configuration 1 Register (Address = 0x09)[Reset = 0x18]
        1. Table 19. Bias Configuration 1 Register Field Descriptions
      10. 7.6.10 Bias Configuration 2 register (Address = 0x0A)[Reset = 0x11]
        1. Table 20. Bias Configuration 2 Register Field Descriptions
      11. 7.6.11 Bias Configuration 3 Register (Address = 0x0B)[Reset = 0x00]
        1. Table 21. Bias Configuration 3 Register Field Descriptions
      12. 7.6.12 LCM Boost Bias Register (Address = 0x0C)[Reset = 0x28]
        1. Table 22. LCM Boost Bias Register Field Descriptions
      13. 7.6.13 VPOS Bias Register (Address = 0x0D)[Reset = 0x1E]
        1. Table 23. VPOS Bias Register Field Descriptions
      14. 7.6.14 VNEG Bias Register (Address = 0x0E)[Reset = 0x1C]
        1. Table 24. VNEG Bias Register Field Descriptions
      15. 7.6.15 Flags Register (Address = 0x0F)[Reset = 0x00]
        1. Table 25. Flags Register Field Descriptions
      16. 7.6.16 Option 1 Register (Address = 0x10)[Reset = 0x06]
        1. Table 26. Option 1 Register Field Descriptions
      17. 7.6.17 Option 2 Register (Address = 0x11)[Reset = 0x35]
        1. Table 27. Option 2 Register Field Descriptions
      18. 7.6.18 PWM-to-Digital Code Readback LSB Register (Address = 0x12)[Reset = 0x00]
        1. Table 28. PWM-to-Digital Code Readback LSB Register Field Descriptions
      19. 7.6.19 PWM-to-Digital Code Readback MSB Register (Address = 0x13)[Reset = 0x00]
        1. Table 29. PWM-to-Digital Code Readback MSB Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Boost Output Capacitor Selection
          3. 8.2.2.1.3 Input Capacitor Selection
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Backlight Curves
          1. 8.2.3.1.1 Two LED Strings
          2. 8.2.3.1.2 Three LED Strings
        2. 8.2.3.2 LCM Bias Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Unless otherwise specified, typical limits apply at 25°C, minimum and maximum limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C), and VIN = 3.6 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
ISD Shutdown current HWEN = 0 0.2 2.8 µA
IQ Quiescent current, device not switching HWEN = VIN, LCM  boost disabled 1 7 µA
ILCM_EN Bias power no load supply current VPOS, VNEG enabled with no load, backlight boost disabled, typical application circuit (not ATE tested) 0.5 10 µA
BACKLIGHT LED CURRENT SINKS (LED1, LED2, LED3, LED4)
ILED_MAX Maximum output current (per string) 2.7 V ≤ VIN ≤ 5 V, linear or exponential mode 30 mA
ILED LED current accuracy(1) 2.7 V ≤ VIN ≤ 5 V, 60 µA < ILED< 30 mA, linear or exponential mode –3% 3%
IMATCH ILED current matching(2) 2.7 V ≤ VIN ≤ 5 V, 60 µA ≤ ILED ≤ 30 mA, linear or exponential mode –2% 0.2% 2%
ILED_MIN Minimum LED current (per string) Linear or exponential mode 60 µA
ISTEP LED current step size (code to code) Exponential mode(3) 0.3%
Linear mode 14.63 µA
BACKLIGHT BOOST
OVP threshold ON threshold, 2.7 V ≤ VIN ≤ 5 V 011 to 111 28.5 29 29.5 V
010 24.5 25 25.5
001 20.5 21 21.5
000 16.3 17 17.7
OVP hysteresis OFF threshold 0.5 V
Efficiency Boost efficiency VIN = 3.6 V, IBLED = 5 mA/string, (POUT/PIN), Typical Application Circuit (not ATE tested) 90%
VHR Regulated current-sink headroom voltage (boost feedback voltage) ILED = 30 mA 310 mV
ILED = 5 mA 120 mV
VHR_MIN Current-sink minimum headroom voltage ILED = 95% of nominal, ILED = 5 mA 30 50 mV
RDSON NMOS switch on resistance ISW = 250 mA 0.2 Ω
ICL NMOS switch current limit 2.7 V ≤ VIN ≤ 5 V 00 792 900 1008 mA
01 1056 1200 1344 mA
10 1320 1500 1680 mA
11 1584 1800 2016 mA
ƒBL_SW Switching frequency 2.7 V ≤ VIN ≤ 5 V 500-kHz mode 450 500 550 kHz
1-MHz mode 900 1000 1100
DMAX Maximum duty cycle VIN = 2.7 V, ƒLED_SW = 1 MHz 93% 94%
DEVICE PROTECTION
TSD Thermal shutdown Not ATE tested 140 °C
DISPLAY BIAS (LCM BOOST)
VOVP_LCM LCM bias boost overvoltage protection On threshold, 2.7 V ≤ VIN ≤ 5 V 7.8 V
ƒLCM_SW Switching frequency(6) 2.7 V ≤ VIN ≤ 5 V (continuous conduction mode) 2500 kHz
VLCM_OUT LCM boost output voltage range 4 7.15 V
Efficiency VIN = 3.6 V, VLCM_OUT = 5.9 V, 6 mA < ILCM_OUT< 160mA, Typical Application Circuit (not ATE tested) 92%
Output voltage step size 50 mV
ILCM_BOOST_CL Valley current limit 1000 mA
RDSON_LCM High-side MOSFET on resistance VIN = VGS = 3.6 V 170 mΩ
Low-side MOSFET on Resistance VIN = VGS = 3.6 V 290
VLCM_OUT_ RIPPLE Peak-to-peak ripple voltage(6) ILOAD_LCM_BOOST = 5 mA and 50 mA, CBST = 20 µF 50 mVpp
VLCM_OUT_LINE_ TRANSIENT LCM_OUT line transient response(6) VIN + 500 mVp-p AC square wave, Tr = 100 mV/µs, 200 Hz, 12.5% DS at 5 mA, ILOAD = 5 mA, CIN = 10 µF –50 ±25 50 mV
VLCM_OUT_LOAD_ TRANSIENT LCM_OUT load transient response(6) 0 mA to 150 mA, tRISE/FALL = 100 mA/µs,
CIN = 10 µF		 –150 150 mV
tLCM_OUT_ST Start-up time (LCM_OUT), VLCM_OUT = 10% to 90%(6) CLCM_OUT = 20 µF 1000 µs
DISPLAY BIAS POSITIVE OUTPUT (VPOS)
VVPOS Programmable output voltage range 4 6.5 V
Output voltage step size 50 mV
Output voltage accuracy Output voltage = 5.4 V –1.5% 1.5%
IVPOS_MAX Maximum output current 80 mA
IVPOS_CL Output current limit 180 mA
IRUSH_PK_VPOS Peak start-up inrush current(6) VLCM_OUT = 6.3 V, VPOS = 5.8 V, CVPOS = 10 µF (nominal) 250 mA
VVPOS_LINE_TRANSIENT LDO_VPOS line transient response(6) VIN + 500 mVp-p AC square wave, Tr = 100 mV/µs, 200 Hz at 25 mA, CIN = 10 µF (nominal) –50 50 mV
VVPOS_LOAD_TRANSIENT LDO_VPOS load transient response(6) Load current step 0 mA to 50 mA, CVPOS = 10 µF (nominal) –50 50 mV
VVPOS_DC_REG DC load regulation(6) 0 mA ≤ ILOAD_VPOS ≤ ILOAD_VPOS_MAX 20 mV
VDO_VPOS VPOS dropout voltage(5) ILOAD_VPOS = ILOAD_VPOS_MAX
VVPOS = 5.7 V		 160 mV
PSSRVPOS Power supply rejection ratio (LDO_VPOS)(6) ƒ = 10 Hz to 500 kHz at IMAX/2
VLCM_OUT – VVPOS ≥ 300 mV		 25 dB
tST_VPOS Start-up time (LDO_VPOS)(4)
VVPOS = 10% to 90%(6) 		CVPOS = 10 µF v 800 µs
RPD_VPOS Output pulldown resistor (VPOS) VPOS pulldown in shutdown 30 80 270 Ω
Pulldown resistance on LCM_EN1 Not ATE tested 300 kΩ
DISPLAY BIAS NEGATIVE OUTPUT (VNEG)
VNEG_SHORT NEG output short circuit protection VNEG to CP_GND, VNEG rises to % of target 84%
VVNEG Efficiency(4) VLCM_OUT = 5.7 V, VNEG = –5.4 V, INEG> –5 mA 92%
Programmable output voltage range –6.5 –4 V
Output voltage step size 50 mV
Output accuracy Output voltage = –5.4 V –1.5% 1.5%
ILOAD_VNEG_MAX Maximum output current VLCM_OUT = 5.9 V, VNEG = –5.4 V 80 mA
IVNEG_CL Output current limit 135 mA
RDSON_VNEG CP FET ON resistance Q1 350 mΩ
Q2 240
Q3 240
VVNEG_RIPPLE Peak-to-peak ripple voltage(6) INEG = –5 mA and –50 mA,
CVNEG = 10 µF (nominal)		 60 mVpp
VVNEG_LINE_TRANSIENT VNEG line transient response(6) VIN + 500 mVp-p AC square wave, 100 mV/µs 200 Hz,
12.5% duty at 5 mA		 –50 ±25 50 mV
VVNEG_LOAD_TRANSIENT VVNEG load transient response(6) 0 to –50 mA step, tRISE/FALL = 1 µs, CVNEG = 10 µF (nominal) 100 mV
tSU_VNEG VVNEG start-up time, VVNEG = 10% to 90%(6) VVNEG = –6.5 V, CVNEG = 10 µF (nominal) 1 ms
RVNEG Output pullup resistor (VNEG to CP_GND)(6) VNEG pullup in shutdown 6 20 Ω
Pulldown resistance on LCM_EN2 Not ATE tested 300 kΩ
PWM INPUT
ƒPWM_INPUT PWM input frequency(4) 2.7 V ≤ VIN ≤ 5 V 50 50000 Hz
tMIN_ON Minimum pulse ON time(6) 24-MHz sample rate 183.3 ns
4-MHz sample rate 1100
1-MHz sample rate 4400
tMIN_OFF Minimum pulse OFF timet(6) 24-MHz sample rate 183.3 ns
4-MHz sample rate 1100
1-MHz sample rate 4400
tSTART-UP Turnon delay from PWM = 0 to PWM = 50% duty cycle 4-MHz sample rate 3.5 ms
PWMRES PWM input resolution 50 Hz < ƒPWM< 11 kHz 11 bits
tGLITCH PWM input glitch rejection Filter = 00 0 ns
Filter = 01 100
Filter = 10 150
Filter = 11 200
LOGIC INPUTS (PWM, HWEN, EN_POS, EN_NEG, SCL, SDA, EN_BL)
VIL Input logic low 2.7 V ≤ VIN ≤ 5 V 0 0.4 V
VIH Input logic high 2.7 V ≤ VIN ≤ 5 V 1.2 VIN V
LOGIC OUTPUTS (SDA)
VOL Output logic low 2.7 V ≤ VIN ≤ 5 V, IOL = 3 mA 0.4 V
(1) Output current accuracy is the difference between the actual value of the output current and programmed value of this current.
(2) LED current matching is the maximum difference between any string current and the average string current, divided by the average string current. This is calculated as (ILEDX – ILED_AVE) / ILED_AVE × 100.
(3) LED current step size from code to code in exponential mode is typically 0.304%, given as (1 – (ILED(CODE+1) / ILED(CODE)).
(4) Typical value only for information.
(5) VIN_VPOS – VVPOS when VVPOS has dropped 100 mV below target.
(6) Limits set by characterization and/or simulation only.