SNVSCV4 September   2024 LM3645

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Amplifier Synchronization (TORCH/TX)
      2. 6.3.2 Input Voltage Flash Monitor (IVFM)
      3. 6.3.3 Fault/Protections
        1. 6.3.3.1  Fault Operation
        2. 6.3.3.2  Flash Time-Out
        3. 6.3.3.3  Overvoltage Protection (OVP)
        4. 6.3.3.4  Current Limit
        5. 6.3.3.5  NTC Thermistor Input/Outputs (TEMP1, TEMP2)
        6. 6.3.3.6  Thermal Scale Back
        7. 6.3.3.7  Thermal Shutdown (TSD)
        8. 6.3.3.8  Undervoltage Lockout (UVLO)
        9. 6.3.3.9  LED and/or VOUT Short Fault
        10. 6.3.3.10 Fault Behavior Table
    4. 6.4 Device Functioning Modes
      1. 6.4.1 Flash Mode
      2. 6.4.2 Torch Mode
      3. 6.4.3 IR Mode
      4. 6.4.4 Voltage Mode
      5. 6.4.5 Mode Transitions
      6. 6.4.6 Boost Operation
        1. 6.4.6.1 Start-Up (Enabling The Device)
        2. 6.4.6.2 Pass Mode
        3. 6.4.6.3 Output Voltage Regulation
    5. 6.5 Programming and Control
      1. 6.5.1 Dx_EN Bits
      2. 6.5.2 STR1 and STR2 Usage
      3. 6.5.3 TOR/TX Usage
      4. 6.5.4 Control State Diagram
      5. 6.5.5 I2C-Compatible Interface
        1. 6.5.5.1 Data Validity
        2. 6.5.5.2 Start and Stop Conditions
        3. 6.5.5.3 Transferring Data
        4. 6.5.5.4 I2C-Compatible Chip Address
    6. 6.6 Register Descriptions
      1. 6.6.1 MainReg Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Output Control Examples
        1. 7.2.2.1 Four Channel Flash with Strobe1 Trigger Starting in Standby
        2. 7.2.2.2 Four Channel Flash with Strobe1 Trigger Starting in I2C Torch
        3. 7.2.2.3 Mixed Mode Functionality
        4. 7.2.2.4 Voltage Mode Only
        5. 7.2.2.5 Voltage Mode With Advanced IR
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Snubber Requirement
        2. 7.2.3.2 Output Capacitor Selection
        3. 7.2.3.3 Input Capacitor Selection
        4. 7.2.3.4 Inductor Selection
      4. 7.2.4 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5.5.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LM3645 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LM3645 generates an acknowledge after each byte is received. There is no acknowledge created after data is read from the device.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LM3645 7-bit address is 0x65. For the eighth bit, a '0' indicates a WRITE and a '1' indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register.

LM3645 Write Cycle W = Write (SDA = "0") R = Read (SDA = "1") Ack = Acknowledge (SDA Pulled Down by Either Master or Slave) ID = Chip Address, 65h for LM3645Figure 6-13 Write Cycle W = Write (SDA = "0") R = Read (SDA = "1") Ack = Acknowledge (SDA Pulled Down by Either Master or Slave) ID = Chip Address, 65h for LM3645