JAJSH28D November   2013  – March 2019 LM3697

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      昇圧効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 PWM Input
      2. 7.1.2 HWEN Input
      3. 7.1.3 Thermal Shutdown
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1 High-Voltage LED Control
        1. 7.3.1.1 High-Voltage Boost Converter
        2. 7.3.1.2 High-Voltage Current Sinks (HVLED1, HVLED2 and HVLED3)
        3. 7.3.1.3 High-Voltage Current String Biasing
      2. 7.3.2 Boost Switching-Frequency Select
      3. 7.3.3 Automatic Switching Frequency Shift
      4. 7.3.4 Brightness Register Current Control
        1. 7.3.4.1 8-Bit Control (Preferred)
        2. 7.3.4.2 11-Bit Control
      5. 7.3.5 PWM Control
        1. 7.3.5.1 PWM Input Frequency Range
        2. 7.3.5.2 PWM Input Polarity
        3. 7.3.5.3 PWM Zero Detection
      6. 7.3.6 Start-up/Shutdown Ramp
      7. 7.3.7 Run-Time Ramp
      8. 7.3.8 High-Voltage Control A and B Ramp Select
    4. 7.4 Device Functional Modes
      1. 7.4.1 LED Current Mapping Modes
        1. 7.4.1.1 Exponential Mapping
          1. 7.4.1.1.1 8-Bit Code Calculation
          2. 7.4.1.1.2 11-Bit Code Calculation
        2. 7.4.1.2 Linear Mapping
          1. 7.4.1.2.1 8-Bit Code Calculation
          2. 7.4.1.2.2 11-Bit Code Calculation
      2. 7.4.2 Fault Flags/Protection Features
        1. 7.4.2.1 Open LED String (HVLED)
        2. 7.4.2.2 Shorted LED String (HVLED)
        3. 7.4.2.3 Overvoltage Protection (Inductive Boost)
        4. 7.4.2.4 Current Limit (Inductive Boost)
      3. 7.4.3 I2C-Compatible Interface
        1. 7.4.3.1 Start And Stop Conditions
        2. 7.4.3.2 I2C-Compatible Address
        3. 7.4.3.3 Transferring Data
        4. 7.4.3.4 High-Speed Mode
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Boost Converter Maximum Output Power
          1. 8.2.2.1.1 Peak Current Limited
          2. 8.2.2.1.2 Output Voltage Limited
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Schottky Diode Selection
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 Application Circuit Component List
      3. 8.2.3 Application Performance Plots
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Boost Output Capacitor Placement
      2. 10.1.2 Schottky Diode Placement
      3. 10.1.3 Inductor Placement
      4. 10.1.4 Boost Input Capacitor Placement
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • YFQ|12
サーマルパッド・メカニカル・データ
発注情報

10.1.3 Inductor Placement

The node where the inductor connects to the LM3697 device’s SW pin has 2 issues. First, a large switched voltage (0 to VOUT + VF_SCHOTTKY) appears on this node every switching cycle. This switched voltage can be capacitively coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces connecting the input supply to the inductor and connecting the inductor to the SW pin. Any resistance in this path can cause voltage drops that can negatively affect efficiency and reduce the input operating voltage range.

To reduce the capacitive coupling of the signal on SW into nearby traces, the SW pin-to-inductor connection must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, high-impedance nodes that are more susceptible to electric field coupling need to be routed away from SW and not directly adjacent or beneath. This is especially true for traces such as SCL, SDA, HWEN, and PWM. A GND plane placed directly below SW dramatically reduces the capacitance from SW into nearby traces.

Lastly, limit the trace resistance of the VIN-to-inductor connection and from the inductor to SW connection, by use of short, wide traces.