JAJSLV2 October   2022 LM5012-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Architecture
      2. 8.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 8.3.3  Regulation Comparator
      4. 8.3.4  Internal Soft Start
      5. 8.3.5  On-Time Generator
      6. 8.3.6  Current Limit
      7. 8.3.7  N-Channel Buck Switch and Driver
      8. 8.3.8  Schottky Diode Selection
      9. 8.3.9  Enable/Undervoltage Lockout (EN/UVLO)
      10. 8.3.10 Power Good (PGOOD)
      11. 8.3.11 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Switching Frequency (RRON)
        3. 9.2.2.3 Buck Inductor (LO)
        4. 9.2.2.4 Output Capacitor (COUT)
        5. 9.2.2.5 Input Capacitor (CIN)
        6. 9.2.2.6 Type 3 Ripple Network
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Compact PCB Layout for EMI Reduction
        2. 9.4.1.2 Feedback Resistors
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

TJ = –40°C to +150°C, VIN = 24 V. Typical values are at TJ = 25°C and VEN/UVLO = 2 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IQ-SHUTDOWN VIN shutdown current VEN/UVLO = 0V 3.1 9.9 µA
IQ-SLEEP VIN sleep current VEN = 2.5 V, VFB = 1.5 V, VBST –VSW = 5 V, non-switching 10 20 µA
IQ-STANDBY VIN standby current VEN =  1.2 V 25 40 µA
IQ-ACTIVE VIN Active current VEN =  2.5 V 450 µA
EN/UVLO
VSD-RISING Shutdown threshold 1.1 V
VSD-FALLING Shutdown threshold  0.45 V
VEN-RISING EN threshold rising 1.43 1.5 1.6 V
VEN-FALLING EN threshold falling 1.35 1.4 1.47 V
FEEDBACK VOLTAGE
VREF FB regulation voltage 1.181 1.2 1.218 V
TIMING
tON1 On-time1 VVIN = 12 V, RRON = 75 kΩ 2550 ns
tON2 On-time2 VVIN = 12 V, RRON = 25 kΩ 830 ns
tON3 On-time3 VVIN = 48 V, RRON = 75 kΩ 625 ns
tON4 On-time4 VVIN = 48 V, RRON = 25 kΩ 245 ns
tON5 On-time5 VVIN = 100 V, RRON = 75 kΩ 330 ns
tON6 On-time6 VVIN = 100 V, RRON = 25 kΩ 128 ns
PGOOD
VPG-UTH FB upper threshold for PGOOD low to high VFB rising 1.1 1.14 1.2 V
VPG-LTH FB lower threshold for PGOOD high to low VFB falling 1.05 1.08 1.12 V
VPG-HYS PGOOD upper and lower threshold hysteresis VFB falling 60 mV
RPG PGOOD pulldown resistance VFB = 1 V 8 Ω
BOOTSTRAP
VBST-UV Gate drive UVLO VBST falling 2.4 3.4 V
POWER SWITCH
RDSON-HS High-side MOSFET RDSON ISW = –100 mA 0.25 Ω
SOFT START
tSS Internal soft-start 1.75 3.5 4.75 ms
CURRENT LIMIT
IPEAK  Peak current limit threshold 2.8 3.2 3.6 A
THERMAL SHUTDOWN
TJ-SD Thermal shutdown threshold (1) Temperature rising 175 °C
TJ-HYS Thermal shutdown hysteresis (1) 10 °C
(1) Specified by design. Not product tested.