JAJSO81 October   2022 LM5013

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings_Catalog
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristivcs
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Architecture
      2. 8.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 8.3.3  Regulation Comparator
      4. 8.3.4  Internal Soft Start
      5. 8.3.5  On-Time Generator
      6. 8.3.6  Current Limit
      7. 8.3.7  N-Channel Buck Switch and Driver
      8. 8.3.8  Schottky Diode Selection
      9. 8.3.9  Enable and Undervoltage Lockout (EN/UVLO)
      10. 8.3.10 Power Good (PGOOD)
      11. 8.3.11 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Sleep Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Switching Frequency (RRON)
        3. 9.2.2.3 Buck Inductor (LO)
        4. 9.2.2.4 Schottky Diode (DSW)
        5. 9.2.2.5 Output Capacitor (COUT)
        6. 9.2.2.6 Input Capacitor (CIN)
        7. 9.2.2.7 Type 3 Ripple Network
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Compact PCB Layout for EMI Reduction
        2. 9.4.1.2 Feedback Resistors
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Control Architecture

The LM5012 step-down switching converter employs a constant on-time (COT) control scheme. The COT control scheme sets a fixed on time, tON, of the high-side FET using a timing resistor (RON). tON is adjusted as VIN changes and is inversely proportional to the input voltage to maintain a fixed frequency when in continuous conduction mode (CCM). After tON expires, the high-side FET remains off until the feedback pin is equal or below the 1.2-V reference voltage. To maintain stability, the feedback comparator requires a minimal ripple voltage that is in-phase with the inductor current during the off time. Furthermore, this change in feedback voltage during the off time must be large enough to dominate any noise present at the feedback node. The minimum recommended feedback ripple voltage is 20 mV. See Table 8-1 for different types of ripple injection schemes that ensure stability over the full input voltage range.

During a rapid start-up or a positive load step, the regulator operates with minimum off times until regulation is achieved. This feature enables extremely fast load transient response with minimum output voltage undershoot. When regulating the output in steady-state operation, the off time automatically adjusts itself to produce the SW-pin duty cycle required for output voltage regulation to maintain a fixed switching frequency. In CCM, the switching frequency, FSW, is programmed by the RRON resistor. Use Equation 2 to calculate the switching frequency.

Equation 1. GUID-A5DCE4E1-C8B2-47FC-8825-22678B152C08-low.gif
Table 8-1 Ripple Generation Methods
Type 1Type 2Type 3
Lowest CostReduced RippleMinimum Ripple
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Table 8-1 presents three different methods for generating appropriate voltage ripple at the feedback node. Type-1 ripple generation method uses a single resistor, RESR, in series with the output capacitor. The generated voltage ripple has two components: capacitive ripple caused by the inductor ripple current charging and discharging the output capacitor and resistive ripple caused by the inductor ripple current flowing into the output capacitor and through series resistance, RESR. The capacitive ripple component is out-of-phase with the inductor current and does not decrease monotonically during the off time. The resistive ripple component is in-phase with the inductor current and decreases monotonically during the off time. The resistive ripple must exceed the capacitive ripple at VOUT for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT converters with multiple on-time bursts in close succession followed by a long off time. The lowest cost bill of materials (BOM) define the value of the series resistance RESR to ensure sufficient in-phase ripple at the feedback node.

Type-2 ripple generation uses a CFF capacitor in addition to the series resistor. As the output voltage ripple is directly AC-coupled by CFF to the feedback node, the RESR and ultimately the output voltage ripple, are reduced by a factor of VOUT / VFB1.

Type-3 ripple generation uses an RC network consisting of RA and CA, and the switch node voltage to generate a triangular ramp that is in-phase with the inductor current. This triangular wave is the AC-coupled into the feedback node with capacitor CB. Because this circuit does not use output voltage ripple, it is suited for applications where low output voltage ripple is critical. The Selecting an Ideal Ripple Generation Network for Your COT Buck Converter application report provides additional details on this topic.

Note: For all methods specified, 12 mV is the minimum FB ripple voltage. 20 mV is calculated as a conservative figure. For wide-VIN ranges, calculating for 20 mV can be insufficient to achieve 12-mV FB ripple at minimum input voltage. Careful evaluation should be done to ensure the minimum ripple requirement is fulfilled, or the design can be faced with large output ripple, irregular switching at the application minimum output voltage.