JAJSO81 October   2022 LM5013

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings_Catalog
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristivcs
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Architecture
      2. 8.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 8.3.3  Regulation Comparator
      4. 8.3.4  Internal Soft Start
      5. 8.3.5  On-Time Generator
      6. 8.3.6  Current Limit
      7. 8.3.7  N-Channel Buck Switch and Driver
      8. 8.3.8  Schottky Diode Selection
      9. 8.3.9  Enable and Undervoltage Lockout (EN/UVLO)
      10. 8.3.10 Power Good (PGOOD)
      11. 8.3.11 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Switching Frequency (RRON)
        3. 9.2.2.3 Buck Inductor (LO)
        4. 9.2.2.4 Schottky Diode (DSW)
        5. 9.2.2.5 Output Capacitor (COUT)
        6. 9.2.2.6 Input Capacitor (CIN)
        7. 9.2.2.7 Type 3 Ripple Network
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Compact PCB Layout for EMI Reduction
        2. 9.4.1.2 Feedback Resistors
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.7 Type 3 Ripple Network

A Type 3 ripple generation network uses an RC filter consisting of RA and CA across SW and VOUT to generate a triangular ramp that is in phase with the inductor current. This triangular ramp is then AC-coupled into the feedback node using capacitor CB as shown in Figure 9-1. Type 3 ripple injection is suited for applications where low output voltage ripple is crucial.

Use Equation 16 and Equation 17 to calculate RA and CA to provide the required ripple amplitude at the FB pin.

Equation 16. GUID-FA3D56A2-F985-4165-A96A-2E97B8F640C4-low.gif

For the feedback resistor RFBT = 453 kΩ and RFBB = 49.9 kΩ values shown in Figure 9-1, Equation 16 dictates a minimum CA of 742 pF. In this design, a 3300-pF capacitance is chosen. This value is chosen to keep RA within practical limits between 100 kΩ and 1 MΩ when using Equation 17.

Equation 17. Ra ×Ca≤VINnom-VOUT×tONnom 20mV

Based on CA set at 3.3 nF, RA is calculated to be 453 kΩ to provide a 20-mV ripple voltage at FB. The general recommendation for a Type 3 network is to calculate RA and CA to get 20 mV of ripple at typical operating conditions. A smaller RA can need to be used to operate below nominal 48-V input. Ensure 12 mV of FB ripple or more at the minimum input voltage design to ensure stability.

While the amplitude of the generated ripple does not affect the output voltage ripple, it impacts the output regulation as it reflects as a DC error of approximately half the amplitude of the generated ripple. For example, a converter circuit with Type 3 network that generates a 40-mV ripple voltage at the feedback node has approximately 10-mV worse load regulation scaled up through the FB divider to VOUT than the same circuit that generates a 20-mV ripple at FB. Use Equation 18 to calculate the coupling capacitance, CB.

Equation 18. GUID-8231E7C9-5916-4A53-A087-EF524037F99A-low.gif

where

  • tTR-settling is the desired load transient response settling time.

CB calculates to 56 pF based on a 75-µs settling time. This value avoids excessive coupling capacitor discharge by the feedback resistors during sleep intervals when operating at light loads. To avoid capacitance fall-off with DC bias, use a C0G or NP0 dielectric capacitor for CB.