JAJSO81 October   2022 LM5013

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings_Catalog
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristivcs
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Architecture
      2. 8.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 8.3.3  Regulation Comparator
      4. 8.3.4  Internal Soft Start
      5. 8.3.5  On-Time Generator
      6. 8.3.6  Current Limit
      7. 8.3.7  N-Channel Buck Switch and Driver
      8. 8.3.8  Schottky Diode Selection
      9. 8.3.9  Enable and Undervoltage Lockout (EN/UVLO)
      10. 8.3.10 Power Good (PGOOD)
      11. 8.3.11 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Switching Frequency (RRON)
        3. 9.2.2.3 Buck Inductor (LO)
        4. 9.2.2.4 Schottky Diode (DSW)
        5. 9.2.2.5 Output Capacitor (COUT)
        6. 9.2.2.6 Input Capacitor (CIN)
        7. 9.2.2.7 Type 3 Ripple Network
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Compact PCB Layout for EMI Reduction
        2. 9.4.1.2 Feedback Resistors
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.6 Input Capacitor (CIN)

An input capacitor is necessary to limit the input ripple voltage while providing AC current to the buck power stage at every switching cycle. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the VIN and GND pins of the LM5013. The input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. The device follows that the resultant capacitive component of AC ripple voltage is a triangular waveform.

Along with the ESR-related ripple component, use Equation 14 to calculate the peak-to-peak ripple voltage amplitude.

Equation 14. GUID-DA0EDF58-3FCF-49A2-B0B7-2752F1B714F9-low.gif

Use Equation 15 to calculate the input capacitance required for a load current, based on an input voltage ripple specification (ΔVIN).

Equation 15. GUID-C98A09F9-AF5E-458A-A260-E5067BE9F61E-low.gif

The recommended high-frequency input capacitance is 4.4 µF or higher. Ensure the input capacitor is a high-quality X7S or X7R ceramic capacitor with sufficient voltage rating for CIN. Based on the voltage coefficient of ceramic capacitors, choose a voltage rating preferably twice the maximum input voltage. Additionally, some bulk capacitance can be required for large input loop inductance or long wire harnesses used in the system. This capacitor provides parallel damping to the resonance associated with parasitic inductance of the supply lines and high-Q ceramics. See the Power Supply Recommendations section for more detail.