JAJSAO5I January   2007  – December 2017 LM5022

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-Voltage Start-Up Regulator
      2. 7.3.2 Input Undervoltage Detector
      3. 7.3.3 Error Amplifier
      4. 7.3.4 Current Sensing and Current Limiting
      5. 7.3.5 PWM Comparator and Slope Compensation
      6. 7.3.6 Soft Start
      7. 7.3.7 MOSFET Gate Driver
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Oscillator, Shutdown, and SYNC
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  MOSFET
        3. 8.2.2.3  Output Diode
        4. 8.2.2.4  Boost Inductor
        5. 8.2.2.5  Output Capacitor
        6. 8.2.2.6  VCC Decoupling Capacitor
        7. 8.2.2.7  Input Capacitor
        8. 8.2.2.8  Current Sense Filter
        9. 8.2.2.9  RSNS, RS2 and Current Limit
        10. 8.2.2.10 Control Loop Compensation
        11. 8.2.2.11 Efficiency Calculations
          1. 8.2.2.11.1 Chip Operating Loss
          2. 8.2.2.11.2 MOSFET Switching Loss
          3. 8.2.2.11.3 MOSFET and RSNS Conduction Loss
          4. 8.2.2.11.4 Output Diode Loss
          5. 8.2.2.11.5 Input Capacitor Loss
          6. 8.2.2.11.6 Output Capacitor Loss
          7. 8.2.2.11.7 Boost Inductor Loss
          8. 8.2.2.11.8 Total Loss
          9. 8.2.2.11.9 Efficiency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Filter Capacitors
      2. 10.1.2 Sense Lines
      3. 10.1.3 Compact Layout
      4. 10.1.4 Ground Plane and Shape Routing
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 設計サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Typical limits apply for TJ=25°C and are provided for reference purposes only; minimum and maximum limits apply over the junction temperature (TJ) range of –40°C to 125°C. VIN = 24 V and RT = 27.4 kΩ (unless otherwise noted).(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SYSTEM PARAMETERS
VFB FB pin voltage 1.225 1.25 1.275 V
STARTUP REGULATOR
VCC VCC regulation(2) 10 V ≤ VIN ≤ 60 V, ICC = 1 mA 6.6 7 7.4 V
6 V ≤ VIN< 10V,
VCC Pin Open Circuit		 5
ICC Supply current OUT Pin Capacitance = 0,
VCC = 10 V		 3.5 4 mA
ICC-LIM VCC current limit VCC = 0 V(2)(3) 15 35 mA
VIN - VCC Dropout voltage across bypass switch ICC = 0 mA, ƒSW< 200 kHz,
6 V ≤ VIN ≤ 8.5 V 		200 mV
VBYP-HI Bypass switch turnoff threshold VIN increasing 8.7 V
VBYP-HYS Bypass switch threshold hysteresis VIN Decreasing 260 mV
ZVCC VCC pin output impedance
0 mA ≤ ICC ≤ 5 mA		 VIN = 6 V 58 Ω
VIN = 8 V 53
VIN = 24 V 1.6
VCC-HI VCC pin UVLO rising threshold 5 V
VCC-HYS VCC pin UVLO falling hysteresis 300 mV
IVIN Startup regulator leakage VIN = 60 V 150 500 µA
IIN-SD Shutdown current VUVLO = 0 V, VCC = Open Circuit 350 450 µA
ERROR AMPLIFIER
GBW Gain bandwidth 4 MHz
ADC DC gain 75 dB
ICOMP COMP pin current sink capability VFB = 1.5 V, VCOMP = 1 V 5 17 mA
UVLO
VSD Shutdown threshold 1.22 1.25 1.28 V
ISD-HYS Shutdown hysteresis current source 16 20 24 µA
CURRENT LIMIT
tLIM-DLY Delay from ILIM to output CS steps from 0 V to 0.6 V, OUT transitions to 90% of VCC 30 ns
VCS Current limit threshold voltage 0.45 0.5 0.55 V
tBLK Leading edge blanking time 65 ns
RCS CS pin sink impedance Blanking active 40 75 Ω
SOFT START
ISS Soft-start current source 7 10 13 µA
VSS-OFF Soft start to COMP offset 0.35 0.55 0.75 V
OSCILLATOR
fSW RT to GND = 84.5 kΩ 170(4) 200 230 kHz
RT to GND = 27.4 kΩ See(4) 525 600 675 kHz
RT to GND = 16.2 kΩ See(4) 865 990 1115 kHz
VSYNC-HI Synchronization rising threshold 3.8 V
PWM COMPARATOR
tCOMP-DLY Delay from COMP to OUT transition VCOMP = 2 V, CS stepped
from 0 V to 0.4 V		 25 ns
DMIN Minimum duty cycle VCOMP = 0 V 0%
DMAX Maximum duty cycle 90% 95%
APWM COMP to PWM comparator gain 0.33 V/V
VCOMP-OC COMP pin open circuit voltage VFB = 0 V 4.3 5.2 6.1 V
ICOMP-SC COMP pin short circuit current VCOMP = 0 V, VFB = 1.5 V 0.6 1.1 1.5 mA
SLOPE COMPENSATION
VSLOPE Slope compensation amplitude 83 110 137 mV
MOSFET DRIVER
VSAT-HI Output high saturation voltage (VCC – VOUT) IOUT = 50 mA 0.25 0.75 V
VSAT-LO Output low saturation voltage (VOUT) IOUT = 100 mA 0.25 0.75 V
tRISE OUT pin rise time OUT Pin load = 1 nF 18 ns
tFALL OUT pin fall time OUT Pin load = 1 nF 15 ns
THERMAL CHARACTERISTICS
TSD Thermal shutdown threshold 165 °C
TSD-HYS Thermal shutdown hysteresis 25 °C
(1) All Minimum and Maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD × RθJA) where RθJA (in °C/W) is the package thermal impedance provided in Thermal Information.
(2) VCC provides bias for the internal gate drive and control circuits.
(3) Device thermal limitations may limit usable range.
(4) Specification applies to the oscillator frequency.