7.3.1 High Voltage Start-Up Regulator (VIN and VCC)

The LM5033 contains an internal high-voltage start-up regulator. The input pin (VIN) can be connected directly to line voltages as high as 90 V for normal operation, and can withstand transients to 100 V. The regulator output at VCC, 9.6 V (typical), is internally current limited to 20 mA (minimum). Upon power up, the capacitor at VCC charges up, providing a time delay while internal circuits stabilize. When V_CC reaches the upper threshold of the undervoltage sensor (typically 9.5 V), the undervoltage sensor resets, enabling the output drivers, although the PWM duty cycle is initially at zero. As the soft-start capacitor charges up, the output duty cycle increases until regulated by the PWM control loop. The value of the VCC capacitor which affects the start-up delay depends on the total system design and its start-up characteristics. TI recommends the VCC capacitor to be from 0.1 µF to 50 µF.

The lower threshold of the undervoltage sensor is typically at 6.8 V. If V_CC falls below this value the outputs are disabled and the soft-start capacitor is discharged. When V_CC increases above the upper threshold the outputs are enabled, and the soft-start sequence repeats.

The internal power dissipation of the LM5033 can be reduced by powering VCC from an external supply. Typically this is done by means of an auxiliary transformer winding which is diode connected to the VCC pin to provide 10 V to 15 V as the controller completes the start-up sequence. The externally applied VCC voltage causes the internal regulator to shut off. The undervoltage sensor circuit still functions in this mode, requiring that the external VCC capacitor be sized so that V_CC never falls below 6.8 V. The required current into the VCC pin from the external source is shown in Figure 9.

If a fault condition occurs such that the external supply to VCC fails, external current draw from the VCC pin must be limited to not exceed the current limit of the regulator, or the maximum power dissipation of the IC. An external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the VCC and the VIN pins together and feeding the external bias voltage, 10 V to 15 V, into that node.

7.3.2 Reference (REF)

The REF pin provides a reference voltage of 2.5 V ± 2.4%. The pin is internally connected to an NMOS FET drain at the output of the buffer amplifier, allowing it to sink, but not source current. An external pullup resistor is required. Current into the pin must be limited to less than 20 mA to maintain regulation (see Figure 8).

During start-up if the pullup voltage is present before the reference amplifier establishes regulation, the voltage on REF must not exceed 5.5 V. If this reference is not used the REF pin can float or be connected to ground.

7.3.3 PWM Comparator (COMP), Duty Cycle and Deadtime

The PWM comparator compares an internal ramp signal, 0 V to 0.65 V, with the loop-error voltage derived from the COMP pin. The COMP voltage is typically set by an external error amplifier through an optocoupler for closed-loop applications. Internally, the voltage at the COMP pin passes through two level shifting diodes, and a gain reducing, 3:1 resistor divider. The output of the PWM comparator provides the pulse width information to the output drivers (OUT1 and OUT2). This comparator is optimized for speed to achieve minimum discernable duty cycles. The output duty cycle is 0% for V_COMP < 1.5 V, and maximum for V_COMP > 3.5 V (see Figure 7). The maximum duty cycle for each output is limited to less than 50% due to the forced deadtime. The typical deadtime from the falling edge of one gate driver output to the rising edge of the other gate driver output is 135 ns, and does not vary with frequency. The maximum duty cycle for each output can be calculated with Equation 1.

Equation 1.

where

• t_S is the period of each output
• t_D is the deadtime

For example, if the oscillator frequency is 200 kHz, each output cycles at 100 kHz, and t_S = 10 µs. Using the nominal deadtime of 135 ns, the maximum duty cycle at this frequency is 48.65%. Using the minimum deadtime of 85 ns, the maximum duty cycle increases to 49.15%.

When the SS pin is pulled down, internally or externally, the COMP pin voltage is pulled down with it, with a difference of 0.5 V. When SS voltage increases the COMP voltage is allowed to increase, pulled up by an internal 5.2-V supply through a 5-kΩ resistor.

In an open-loop application, such as an intermediate bus converter, COMP can be left open resulting in maximum duty cycle at the output drivers.

7.3.4 Current Sense (CS)

The current sense circuit is intended to protect the power converter when an abnormal primary current is sensed by initiating a low duty cycle hiccup mode. When the threshold, 0.5 V, at CS is exceeded the outputs are disabled, and the soft-start capacitor is internally discharged. When the soft-start capacitor is fully discharged and the voltage at the CS pin is below 0.5 V, the outputs are re-enabled allowing the soft-start capacitor voltage and the output duty cycle to increase.

The external current sensing circuit must include an RC filter placed near the IC to prevent false triggering of the current sense comparator due to transients or noise. An internal MOSFET discharges the external filter capacitor at the conclusion of each PWM cycle to improve dynamic performance. The discharge time is equal to the deadtime between OUT1 and OUT2 at maximum duty cycle. Additionally, CS is pulled low when V_CC is below the undervoltage threshold or when an overtemperature condition occurs.

7.3.5 Oscillator, Sync Capability (RT/SYNC)

The LM5033 oscillator frequency is set by a single external resistor (R_T) connected between RT/SYNC and ground. The value of the required R_T resistor is calculated with Equation 2.

Equation 2.

where

• F_OSC is the desired oscillator frequency

The outputs (OUT1 and OUT2) alternate at half the oscillator frequency. The voltage at the RT/SYNC pin is internally regulated to a nominal 2 V. The R_T resistor must be placed as close as possible to the IC, and connected directly to the pins (RT/SYNC and GND).

The LM5033 can be synchronized to an external clock by applying a narrow pulse to RT/SYNC. The external clock must be a higher frequency than the free running frequency set by the R_T resistor, and the pulse width must be from 15 ns to 150 ns. The clock signal must be coupled into the RT/SYNC pin through a 100-pF capacitor. When the synchronizing pulse transitions low-to-high, the voltage at RT/SYNC must exceed 3.8 V from its nominal 2-V DC level. During the clock signal low time the voltage at RT/SYNC is clamped at 2 V by an internal regulator. The R_T resistor is always required, whether the oscillator is free running or externally synchronized.

7.3.6 Soft Start (SS)

The soft-start feature allows the converter to gradually reach a steady state operating point, thereby reducing start-up stresses and current surges. Upon turnon, after the undervoltage sensor resets at VCC, an internal 10‑µA current source charges an external capacitor at SS to generate a ramping voltage, 0 V to 5 V, which allows the voltage on the COMP pin to increase gradually. As the COMP voltage increases the output duty cycle increases from zero to the value required for regulation. Internally, the SS pin is pulled low when a current fault is detected at CS, the VCC voltage is below the lower threshold of the under-voltage sensor, or when a thermal shutdown occurs. Additionally, the SS pin can be pulled low by an external device.

In the event of a current fault, the soft-start capacitor is discharged by an internal pulldown device (see Current Sense (CS)). The falling voltage at SS pulls down the COMP pin, ensuring a minimum output duty cycle when the outputs are re-enabled. Then he soft-start capacitor begins to ramp up, allowing the COMP voltage to increase. As the COMP voltage increases, the output duty cycle increases from zero to the value required for regulation. However, if the fault condition is still present the above sequence repeats until the fault is removed.

If the VCC voltage falls below the lower undervoltage sensor threshold, typically 6.8 V, the outputs are disabled, and the soft-start capacitor is discharged. The falling voltage at SS pulls down the COMP pin, thereby ensuring minimum output duty cycle when the outputs are re-enabled. After the VCC voltage increases above the upper threshold, typically 9.5 V, the outputs are enabled, and the soft-start capacitor begins to ramp up, allowing the COMP pin voltage to increase. The output duty cycle then increases from zero to the value required for regulation.

In the event of a fault which results in an excessively high die temperature, an internal thermal shutdown circuit is provided to protect the IC. See Thermal Protection for more information.

Using an externally controlled switch, the outputs (OUT1 and OUT2) can be disabled at any time by pulling SS below 0.5 V. This pulls down the COMP pin to near ground, causing the output duty cycle to go to zero. Upon releasing SS, the soft-start capacitor ramps up, allowing the COMP pin voltage to increase. The output duty cycle then increases from zero to the value required for regulation.

7.3.7 OUT1 and OUT2

The LM5033 provides two alternating outputs, OUT1 and OUT2, each capable of sourcing and sinking 1.5-A peak current. Each toggles at one-half the internal oscillator frequency. The voltage output levels are nominally ground and V_CC, minus a saturation voltage at each level which depends on the current flow.

The outputs can drive power MOSFETs directly in a push-pull application, or they can drive a high voltage gate driver (for example, LM5100) in a bridge application.

The outputs are disabled when any of the following conditions occur:

1. An overcurrent condition is detected at CS.
2. The VCC undervoltage sensor is active.
3. An overtemperature condition is detected.
4. The voltage at SS is below 0.5 V.

7.3.8 Thermal Protection

The system design must limit the LM5033 junction temperature to not exceed 125°C during normal operation. However, in the event of a fault which results in a higher die temperature, an internal thermal shutdown circuit is provided to protect the IC. When thermal shutdown is activated, typically at 165°C, the IC is forced into a low power reset state disabling the output drivers and the VCC regulator. This feature helps prevent catastrophic failures from accidental device overheating. When the die temperature drops below 150°C, typical hysteresis is 15°C, the VCC regulator is enabled and a soft-start sequence initiates.