JAJSJK6D October   2007  – August 2020 LM5067

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Up Sequence
      2. 8.3.2 Gate Control
      3. 8.3.3 Current Limit
      4. 8.3.4 Circuit Breaker
      5. 8.3.5 Power Limit
      6. 8.3.6 Fault Timer and Restart
      7. 8.3.7 Undervoltage Lock-Out (UVLO)
      8. 8.3.8 Overvoltage Lock-Out (OVLO)
      9. 8.3.9 Power Good Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown / Enable Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  RIN, CIN
        2. 9.2.2.2  Current Limit, RS
        3. 9.2.2.3  Power Limit Threshold
        4. 9.2.2.4  Turn-On Time
          1. 9.2.2.4.1 Turn-on With Current Limit Only
          2. 9.2.2.4.2 Turn-on With Power Limit and Current Limit
        5. 9.2.2.5  MOSFET Selection
        6. 9.2.2.6  Timer Capacitor, CT
          1. 9.2.2.6.1 Insertion Delay
          2. 9.2.2.6.2 Fault Timeout Period
          3. 9.2.2.6.3 Restart Timing
        7. 9.2.2.7  UVLO, OVLO
          1. 9.2.2.7.1 Option A:
          2. 9.2.2.7.2 Option B:
          3. 9.2.2.7.3 Option C:
          4. 9.2.2.7.4 Option D:
        8. 9.2.2.8  Thermal Considerations
        9. 9.2.2.9  System Considerations
          1. 9.2.2.9.1 System Considerations During Surge Events
        10. 9.2.2.10 Power Good Pin
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Operating Voltage
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 静電気放電に関する注意事項
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
9.2.2.4.1 Turn-on With Current Limit Only

If the current limit threshold is less than the current defined by the power limit threshold at maximum VDS the circuit operates only at the current limit threshold during turn-on. Referring to Figure 9-5a, as the drain current reaches ILIM, the gate-to-source voltage is controlled at VGSL to maintain the current at ILIM. As the output voltage reaches its final value (VDS ≊ 0 V) the drain current reduces to the value defined by the load, and the gate is charged to approximately 13 V (VGATE). The time for the OUT pin voltage to transition from zero volts to VSYS is equal to:

Equation 4. GUID-429B7051-92CF-42AD-88C4-E06E5DDB2B61-low.gif

where

  • CL is the load capacitance

For example, if VSYS = –48 V, CL = 1000 µF, and ILIM = 1 A, tON calculates to 48 ms. The maximum instantaneous power dissipated in the MOSFET is 48W. This calculation assumes the time from t1 to t2 in Figure 9-5a is small compared to tON, and the load does not draw any current until after the output voltage has reached its final value, and PGD switches high (Figure 9-3).

GUID-835364C6-86B7-44EE-AA79-C9019E8D8081-low.gifFigure 9-3 No Load Current During Turn-on

If the load draws current during the turn-on sequence (Figure 9-4), the turn-on time is longer than the above calculation, and is approximately equal to:

Equation 5. GUID-7D5D1246-E6A5-4D98-9D11-0DD15E9D4737-low.gif

where

  • RL is the load resistance and VSYS is the absolute value of the system input voltage
Note:

The Fault Timeout Period must be set longer than tON to prevent a fault shutdown before the turn-on sequence is complete.

GUID-E32767F2-A5CB-4D16-878A-CDD586C7DC47-low.gifFigure 9-4 Load Draws Current During Turn-On