JAJSJK6D October   2007  – August 2020 LM5067

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Up Sequence
      2. 8.3.2 Gate Control
      3. 8.3.3 Current Limit
      4. 8.3.4 Circuit Breaker
      5. 8.3.5 Power Limit
      6. 8.3.6 Fault Timer and Restart
      7. 8.3.7 Undervoltage Lock-Out (UVLO)
      8. 8.3.8 Overvoltage Lock-Out (OVLO)
      9. 8.3.9 Power Good Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown / Enable Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  RIN, CIN
        2. 9.2.2.2  Current Limit, RS
        3. 9.2.2.3  Power Limit Threshold
        4. 9.2.2.4  Turn-On Time
          1. 9.2.2.4.1 Turn-on With Current Limit Only
          2. 9.2.2.4.2 Turn-on With Power Limit and Current Limit
        5. 9.2.2.5  MOSFET Selection
        6. 9.2.2.6  Timer Capacitor, CT
          1. 9.2.2.6.1 Insertion Delay
          2. 9.2.2.6.2 Fault Timeout Period
          3. 9.2.2.6.3 Restart Timing
        7. 9.2.2.7  UVLO, OVLO
          1. 9.2.2.7.1 Option A:
          2. 9.2.2.7.2 Option B:
          3. 9.2.2.7.3 Option C:
          4. 9.2.2.7.4 Option D:
        8. 9.2.2.8  Thermal Considerations
        9. 9.2.2.9  System Considerations
          1. 9.2.2.9.1 System Considerations During Surge Events
        10. 9.2.2.10 Power Good Pin
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Operating Voltage
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 静電気放電に関する注意事項
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.10 Power Good Pin

During initial power up, the Power Good pin (PGD) is high until the operating voltage (VCC – VEE) increases above ≊2V. PGD then switches low, remaining low as the system voltage and the operating voltage increase. After Q1 is switched on, when the voltage at the OUT pin is within 1.23 V of the SENSE pin (Q1 VDS <1.23 V), PGD switches high indicating the output voltage is at, or nearly at, its final value. Any of the following situations will cause PGD to switch low within ≊10 µs:

  • The VDS of Q1 increases above 2.5 V.
  • The system input voltage decreases below the UVLO level.
  • The system input voltage increase above the OVLO level.
  • The TIMER pin increases to 4V due to a fault condition.

A pull-up resistor is required at PGD as shown in Figure 9-12. The pull-up voltage (VPGD) can be as high as 80 V above VEE, with transient capability to 100 V, and can be higher or lower than the system ground.

GUID-AD49B9F0-D2CA-4D52-86CC-884E419F5D03-low.gifFigure 9-12 Power Good Output

If a delay is required at PGD, suggested circuits are shown in the following figure. In Figure 9-13, capacitor CPG adds delay to the rising edge, but not to the falling edge. In Figure 9-14, the rising edge is delayed by RPG1 + RPG2 and CPG, while the falling edge is delayed a lesser amount by RPG2 and CPG. Adding a diode across RPG2. Figure 9-15 allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge.

GUID-EBF3755E-5543-4B11-9FA7-73B73C159C18-low.gifFigure 9-13 Adding Delay to the Power Good Output Pin - Delay Rising Edge Only
GUID-797AA2DF-E432-43D8-BDA5-E066640F3C7E-low.gifFigure 9-15 Adding Delay to the Power Good Output Pin - Short Delay at Rising Edge and Long Delay at Falling Edge, or Equal Delays
GUID-83B1912F-CC4B-47A0-807F-F16F5FC796FA-low.gifFigure 9-14 Adding Delay to the Power Good Output Pin - Long Delay at Rising Edge, Short Delay at Falling Edge