JAJSGX1G September   2006  – Jaunuary 2020 LM5069

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
    1.     Device Comparison
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Circuit Breaker
      3. 7.3.3 Power Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Overvoltage Lockout (OVLO)
      6. 7.3.6 Power Good Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up Sequence
      2. 7.4.2 Gate Control
      3. 7.4.3 Fault Timer and Restart
      4. 7.4.4 Shutdown Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 48-V, 10-A Hot Swap Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Select RSNS and CL setting
          2. 8.2.1.2.2 Selecting the Hot Swap FET(s)
          3. 8.2.1.2.3 Select Power Limit
          4. 8.2.1.2.4 Set Fault Timer
          5. 8.2.1.2.5 Check MOSFET SOA
          6. 8.2.1.2.6 Set Undervoltage and Overvoltage Threshold
            1. 8.2.1.2.6.1 Option A
            2. 8.2.1.2.6.2 Option B
            3. 8.2.1.2.6.3 Option C
            4. 8.2.1.2.6.4 Option D
          7. 8.2.1.2.7 Input and Output Protection
          8. 8.2.1.2.8 Final Schematic and Component Values
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PC Board Guidelines
      2. 10.1.2 System Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Minimum and maximum limits are specified through test, design, or statistical correlation at TJ= –40°C to 125°C. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. VIN = 48 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT (VIN PIN)
IIN-EN Input current, enabled UVLO > 2.5 V and OVLO < 2.5 V 1.3 1.6 mA
IIN-DIS Input current, disabled UVLO < 2.5 V or OVLO > 2.5 V 480 650 µA
PORIT Power-On reset threshold at VIN to trigger insertion timer VIN increasing 7.6 8 V
POREN Power-On reset threshold at VIN to enable all functions VIN increasing 8.4 9 V
POREN-HYS POREN hysteresis VIN decreasing 90 mV
OUT PIN
IOUT-EN OUT bias current, enabled OUT = VIN, Normal operation 11 µA
IOUT-DIS OUT bias current, disabled(1) Disabled, OUT = 0 V, SENSE = VIN 50
UVLO, OVLO PINS
UVLOTH UVLO threshold 2.45 2.5 2.55 V
UVLOHYS UVLO hysteresis current UVLO = 1 V 12 21 30 µA
UVLODEL UVLO delay Delay to GATE high 55 µs
Delay to GATE low 11
UVLOBIAS UVLO bias current UVLO = 48 V 1 µA
OVLOTH OVLO threshold 2.4 2.5 2.6 V
OVLOHYS OVLO hysteresis current OVLO = 2.6 V 12 21 30 µA
OVLODEL OVLO delay Delay to GATE high 55 µs
Delay to GATE low 11
OVLOBIAS OVLO bias current OVLO = 2.4 V 1 µA
POWER LIMIT (PWR PIN)
PWRLIM-1 Power limit sense voltage (VIN-SENSE) SENSE-OUT = 48 V, RPWR = 150 kΩ 19 25 31 mV
PWRLIM-2 SENSE-OUT = 24 V, RPWR = 75 kΩ 25 mV
IPWR PWR pin current VPWR = 2.5 V 20 µA
GATE CONTROL (GATE PIN)
IGATE Source current Normal operation, GATE-OUT = 5 V 10 16 22 µA
Sink current UVLO < 2.5 V 1.75 2 2.6 mA
VIN to SENSE = 150 mV or VIN < PORIT, VGATE = 5 V 45 110 175 mA
VGATE Gate output voltage in normal operation GATE-OUT voltage 11.4 12 12.6 V
CURRENT LIMIT
VCL Threshold voltage VIN-SENSE voltage 48.5 55 61.5 mV
tCL Response time VIN-SENSE stepped from 0 mV to 80 mV 45 µs
ISENSE SENSE input current Enabled, SENSE = OUT 23 µA
Disabled, OUT = 0 V 60
CIRCUIT BREAKER
VCB Threshold voltage VIN to SENSE 80 105 130 mV
tCB Response time VIN to SENSE stepped from 0 mV to 150 mV, time to GATE low, no load 0.44 1.2 µs
TIMER (TIMER PIN)
VTMRH Upper threshold 3.76 4 4.16 V
VTMRL Lower threshold Restart cycles (LM5069-2) 1.187 1.25 1.313 V
End of 8th cycle (LM5069-2) 0.3 V
Re-enable Threshold (LM5069-1) 0.3 V
ITIMER Insertion time current 3 5.5 8 µA
Sink current, end of insertion time TIMER pin = 2 V 1 1.5 2 mA
Fault detection current 51 85 120 µA
Fault sink current 1.25 2.5 3.75 µA
DCFAULT Fault restart duty cycle LM5069-2 only 0.5%
tFAULT Fault to GATE low delay TIMER pin reaches 4 V 12 µs
POWER GOOD (PGD PIN)
PGDTH Threshold measured at SENSE-OUT Decreasing 0.67 1.25 1.85 V
Increasing, relative to decreasing threshold 0.95 1.25 1.55
PGDVOL Output low voltage ISINK = 2 mA 60 150 mV
PGDIOH Off leakage current VPGD = 80 V 5 µA
(1) OUT bias current (disabled) due to leakage current through an internal 1-MΩ resistance from SENSE to VOUT.