JAJSGX1G September   2006  – Jaunuary 2020 LM5069

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
    1.     Device Comparison
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Circuit Breaker
      3. 7.3.3 Power Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Overvoltage Lockout (OVLO)
      6. 7.3.6 Power Good Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up Sequence
      2. 7.4.2 Gate Control
      3. 7.4.3 Fault Timer and Restart
      4. 7.4.4 Shutdown Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 48-V, 10-A Hot Swap Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Select RSNS and CL setting
          2. 8.2.1.2.2 Selecting the Hot Swap FET(s)
          3. 8.2.1.2.3 Select Power Limit
          4. 8.2.1.2.4 Set Fault Timer
          5. 8.2.1.2.5 Check MOSFET SOA
          6. 8.2.1.2.6 Set Undervoltage and Overvoltage Threshold
            1. 8.2.1.2.6.1 Option A
            2. 8.2.1.2.6.2 Option B
            3. 8.2.1.2.6.3 Option C
            4. 8.2.1.2.6.4 Option D
          7. 8.2.1.2.7 Input and Output Protection
          8. 8.2.1.2.8 Final Schematic and Component Values
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PC Board Guidelines
      2. 10.1.2 System Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.1 Power Up Sequence

The VIN operating range of the LM5069 is 9 V to 80 V, with a transient capability to 100 V. See Functional Block Diagram and Figure 22, as the voltage at VIN initially increases, the external N-channel MOSFET (Q1) is held off by an internal 230-mA pulldown current at the GATE pin. The strong pulldown current at the GATE pin prevents an inadvertent turnon as the MOSFET’s gate-to-drain (Miller) capacitance is charged. Additionally, the TIMER pin is initially held at ground. When the VIN voltage reaches the PORIT threshold (7.6 V) the insertion time begins. During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 5.5-µA current source, and Q1 is held off by a 2-mA pulldown current at the GATE pin regardless of the VIN voltage. The insertion time delay allows ringing and transients at VIN to settle before Q1 can be enabled. The insertion time ends when the TIMER pin voltage reaches 4 V. CT is then quickly discharged by an internal 1.5-mA pulldown current. After the insertion time, the LM5069 control circuitry is enabled when VIN reaches the POREN threshold (8.4 V). The GATE pin then switches on Q1 when VSYS exceeds the UVLO threshold (UVLO pin >2.5 V). If VSYS is above the UVLO threshold at the end of the insertion time, Q1 switches on at that time. The GATE pin charge pump sources 16 µA to charge Q1’s gate capacitance. The maximum gate-to-source voltage of Q1 is limited by an internal 12-V Zener diode.

As the voltage at the OUT pin increases, the LM5069 monitors the drain current and power dissipation of MOSFET Q1. In-rush current limiting and/or power limiting circuits actively control the current delivered to the load. During the in-rush limiting interval (t2 in Figure 22) an internal 85-µA fault timer current source charges CT. If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER pin reaches 4 V, the 85-µA current source is switched off, and CT is discharged by the internal 2.5-µA current sink (t3 in Figure 22). The in-rush limiting interval is complete when the voltage at the OUT pin increases to within 1.25 V of the input voltage (VSYS), and the PGD pin switches high.

If the TIMER pin voltage reaches 4 V before in-rush current limiting or power limiting ceases (during t2), a fault is declared and Q1 is turned off. See Fault Timer and Restart for a complete description of the fault mode.

LM5069 20197213.gifFigure 22. Power-Up Sequence (Current Limit Only)