JAJSGX1G September   2006  – Jaunuary 2020 LM5069

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 改訂履歴
    1.     Device Comparison
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Circuit Breaker
      3. 7.3.3 Power Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Overvoltage Lockout (OVLO)
      6. 7.3.6 Power Good Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up Sequence
      2. 7.4.2 Gate Control
      3. 7.4.3 Fault Timer and Restart
      4. 7.4.4 Shutdown Control
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 48-V, 10-A Hot Swap Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Select RSNS and CL setting
          2. 8.2.1.2.2 Selecting the Hot Swap FET(s)
          3. 8.2.1.2.3 Select Power Limit
          4. 8.2.1.2.4 Set Fault Timer
          5. 8.2.1.2.5 Check MOSFET SOA
          6. 8.2.1.2.6 Set Undervoltage and Overvoltage Threshold
            1. 8.2.1.2.6.1 Option A
            2. 8.2.1.2.6.2 Option B
            3. 8.2.1.2.6.3 Option C
            4. 8.2.1.2.6.4 Option D
          7. 8.2.1.2.7 Input and Output Protection
          8. 8.2.1.2.8 Final Schematic and Component Values
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PC Board Guidelines
      2. 10.1.2 System Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Fault Timer and Restart

When the current limit or power limit threshold is reached during turnon or as a result of a fault condition, the gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation. When either limiting function is activated, an 85-µA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 25 (fault timeout period). If the fault condition subsides during the fault timeout period before the TIMER pin reaches 4 V, the LM5069 returns to the normal operating mode and CT is discharged by the 2.5-µA current sink. If the TIMER pin reaches 4 V during the fault timeout period, Q1 is switched off by a 2-mA pulldown current at the GATE pin. The subsequent restart procedure then depends on which version of the LM5069 is in use.

The LM5069-1 latches the GATE pin low at the end of the fault timeout period. CT is then discharged to ground by the 2.5-µA fault current sink. The GATE pin is held low by the 2-mA pulldown current until a power-up sequence is externally initiated by cycling the input voltage (VSYS), or momentarily pulling the UVLO pin below 2.5 V with an open-collector or open-drain device as shown in Figure 24. The voltage at the TIMER pin must be <0.3 V for the restart procedure to be effective.

LM5069 20197215.gifFigure 24. Latched Fault Restart Control

The LM5069-2 provides an automatic restart sequence which consists of the TIMER pin cycling between 4 V and 1.25 V seven times after the fault timeout period, as shown in Figure 25. The period of each cycle is determined by the 85-µA charging current, and the 2.5-µA discharge current, and the value of the capacitor CT. When the TIMER pin reaches 0.3 V during the eighth high-to-low ramp, the 16-µA current source at the GATE pin turns on Q1. If the fault condition is still present, the fault timeout period and the restart cycle repeat.

LM5069 20197216.gifFigure 25. Restart Sequence (LM5069-2)