JAJSGX1G September   2006  – Jaunuary 2020 LM5069

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
    1.     Device Comparison
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Circuit Breaker
      3. 7.3.3 Power Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Overvoltage Lockout (OVLO)
      6. 7.3.6 Power Good Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up Sequence
      2. 7.4.2 Gate Control
      3. 7.4.3 Fault Timer and Restart
      4. 7.4.4 Shutdown Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 48-V, 10-A Hot Swap Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Select RSNS and CL setting
          2. 8.2.1.2.2 Selecting the Hot Swap FET(s)
          3. 8.2.1.2.3 Select Power Limit
          4. 8.2.1.2.4 Set Fault Timer
          5. 8.2.1.2.5 Check MOSFET SOA
          6. 8.2.1.2.6 Set Undervoltage and Overvoltage Threshold
            1. 8.2.1.2.6.1 Option A
            2. 8.2.1.2.6.2 Option B
            3. 8.2.1.2.6.3 Option C
            4. 8.2.1.2.6.4 Option D
          7. 8.2.1.2.7 Input and Output Protection
          8. 8.2.1.2.8 Final Schematic and Component Values
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PC Board Guidelines
      2. 10.1.2 System Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1.2.1 Select RSNS and CL setting

The LM5069 monitors the current in the external MOSFET (Q1) by measuring the voltage across the sense resistor (RS), connected from VIN to SENSE. When the voltage difference across the VIN and SENSE pins (VCL) is greater than 55 mV (typical), the LM5069 begins modulating the MOSFET gate. Size RSNS for maximum or minimum VCL for applications that require ensured shutoff or ensured conduction. RSNS is sized to exhibit minimum VCL across RSNS at maximum load current in Equation 1.

Equation 1. LM5069 Equation1_SNVS452.gif

Typically sense resistors are only available in discrete value. We choose the next smallest discrete value, 4 mΩ. If a precise current limit is desired, a sense resistor along with a resistor divider can be used as shown in Figure 29.

LM5069 Fig21_ResDiv.gifFigure 29. SENSE Resistor Divider

If using a resistor divider, then the next larger available sense resistor must be chosen (5 mΩ in this example). The ratio of R1 and R2 can then be calculated with Equation 2.

Equation 2. LM5069 Equation2_SNVS452.gif

Note that the SENSE pin pulls 23 µA of current, which creates an offset across R2. TI recommends keeping R2 below 10 Ω to reduce the offset that this introduces. In addition, the 1% resistors add to the current monitoring error. Finally, if the resistor divider approach is used, compute the effective sense resistance (RSNS, EFF) using Equation 3 and use that in all equations instead of RSNS.

Equation 3. LM5069 Equation3_SNVS452.gif

Note that for many applications, a precise current limit may not be required. In that case, it’s simpler to pick the next smaller available sense resistor.