SNOSAW2Q September   2006  – November 2015 LM5100A , LM5100B , LM5100C , LM5101A , LM5101B , LM5101C

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Start-up and UVLO
      2. 8.3.2 Level Shift
      3. 8.3.3 Bootstrap Diode
      4. 8.3.4 Output Stages
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Select Bootstrap and VDD capacitor
        2. 9.2.2.2 Select External Bootstrap Diode and Resistor
        3. 9.2.2.3 Select Gate driver Resistor
        4. 9.2.2.4 Estimate the Driver Power Losses
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

See (1)(2)
MIN MAX UNIT
VDD to VSS −0.3 18 V
HB to HS −0.3 18 V
LI or HI input −0.3 VDD + 0.3 V
LO output −0.3 VDD + 0.3 V
HO output VHS − 0.3 VHB + 0.3 V
HS to VSS (3) −5 100 V
HB to VSS 118 V
Junction temperature 150 °C
Storage temperature −55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military or Aerospace specified devices are required, contact the Texas Instruments Sales Office or Distributors for availability and specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not exceed –1 V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur, the HS voltage must never be more negative than VDD – 15 V. For example if VDD = 10 V, the negative transients at HS must not exceed –5 V.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Machine Model (MM) (2) Option A 50
Option B and C 100
(1) The Human Body Model (HBM) is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. 2 kV for all pins except Pin 2, Pin 3 and Pin 4 which are rated at 1000 V for HBM.
(2) Machine Model (MM) ratings are: 100 V(MM) for Options B and C; 50 V(MM) for Option A.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD 9 14 V
HS –1 100 V
HB VHS + 8 VHS + 14 V
HS slew rate < 50 V/ns
Junction temperature −40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) LM5100A,
LM5100C,
LM5101A		 LM5101C LM5101A LM5100x,
LM5101x 		UNIT
SO PowerPAD MSOP-PowerPAD(3) WSON(3) WSON(3) SOIC
8 PINS 8 PINS 8 PINS 10 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance(2) 40 80 37.8 40 170 °C/W
RθJC(top) Junction-to-case (top) thermal resistance — — 36.7 — — °C/W
RθJB Junction-to-board thermal resistance — — 14.9 — — °C/W
ψJT Junction-to-top characterization parameter — — 0.3 — — °C/W
ψJB Junction-to-board characterization parameter — — 15.2 — — °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — 4.4 — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) The RθJA is not a given constant for the package and depends on the printed circuit board design and the operating environment.
(3) 4-layer board with Cu finished thickness 1.5, 1, 1, 1.5 oz. Maximum die size used. 5× body length of Cu trace on PCB top.
50-mm × 50-mm ground and power planes embedded in PCB. See Application Note AN-1187 (SNOA401).

7.5 Electrical Characteristics

unless otherwise specified, limits are for TJ = 25°C, VDD = VHB = 12 V, VSS = VHS = 0 V, no load on LO or HO (1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD VDD quiescent current, LM5100A/B/C LI = HI = 0 V TJ = 25°C 0.1 mA
TJ = –40°C to 125°C 0.2
VDD quiescent current, LM5101A/B/C LI = HI = 0 V TJ = 25°C 0.25 mA
TJ = –40°C to 125°C 0.4
IDDO VDD operating current f = 500 kHz TJ = 25°C 2 mA
TJ = –40°C to 125°C 3
IHB Total HB quiescent current LI = HI = 0 V TJ = 25°C 0.06 mA
TJ = –40°C to 125°C 0.2
IHBO Total HB operating current f = 500 kHz TJ = 25°C 1.6 mA
TJ = –40°C to 125°C 3
IHBS HB to VSS current, quiescent HS = HB = 100 V TJ = 25°C 0.1 µA
TJ = –40°C to 125°C 10
IHBSO HB to VSS current, operating f = 500 kHz 0.4 mA
INPUT PINS
VIL Input voltage threshold LM5100A/B/C Rising Edge TJ = 25°C 5.4 V
TJ = –40°C to 125°C 4.5 6.3
VIL Input voltage threshold LM5101A/B/C Rising Edge TJ = 25°C 1.8 V
TJ = –40°C to 125°C 1.3 2.3
VIHYS Input voltage hysteresis LM5100A/B/C 500 mV
VIHYS Input voltage hysteresis LM5101A/B/C 50 mV
RI Input pulldown resistance TJ = 25°C 200 kΩ
TJ = –40°C to 125°C 100 400
UNDER VOLTAGE PROTECTION
VDDR VDD rising threshold TJ = 25°C 6.9 V
TJ = –40°C to 125°C 6 7.4
VDDH VDD threshold hysteresis 0.5 V
VHBR HB rising threshold TJ = 25°C 6.6 V
TJ = –40°C to 125°C 5.7 7.1
VHBH HB threshold hysteresis 0.4 V
BOOT STRAP DIODE
VDL Low-current forward voltage IVDD-HB = 100 µA TJ = 25°C 0.52 V
TJ = –40°C to 125°C 0.85
VDH High-current forward voltage IVDD-HB = 100 mA TJ = 25°C 0.8 V
TJ = –40°C to 125°C 1
RD Dynamic resistance LM5100A/B/C, LM5101A/B/C IVDD-HB = 100 mA TJ = 25°C 1.0 Ω
TJ = –40°C to 125°C 1.65
LO AND HO GATE DRIVER
VOL Low-level output voltage LM5100A/LM5101A IHO = ILO = 100 mA TJ = 25°C 0.12 V
TJ = –40°C to 125°C 0.25
Low-level output voltage LM5100B/LM5101B TJ = 25°C 0.16 V
TJ = –40°C to 125°C 0.4
Low-level output voltage LM5100C/LM5101C TJ = 25°C 0.28 V
TJ = –40°C to 125°C 0.65
VOH High-level output voltage LM5100A/LM5101A IHO = ILO = 100 mA
VOH = VDD– LO or
VOH = HB - HO		 TJ = 25°C 0.24 V
TJ = –40°C to 125°C 0.45
High-level output voltage LM5100B/LM5101B TJ = 25°C 0.28 V
TJ = –40°C to 125°C 0.60
High-level output voltage LM5100C/LM5101C TJ = 25°C 0.6 V
TJ = –40°C to 125°C 1.10
IOHL Peak pullup current LM5100A/LM5101A HO, LO = 0 V TJ = 25°C 3 A
Peak pullup current LM5100B/LM5101B 2 A
Peak pullup current LM5100C/LM5101C 1 A
IOLL Peak pulldown current LM5100A/LM5101A HO, LO = 12 V TJ = 25°C 3 A
Peak pulldown current LM5100B/LM5101B 2 A
Peak pulldown current LM5100C/LM5101C 1 A
(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

7.6 Switching Characteristics

Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO (1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tLPHL LO turnoff propagation delay LM5100A/B/C LI Falling to LO Falling 20 45 ns
LO turnoff propagation delay LM5101A/B/C 22 56 ns
tLPLH LO turnon propagation delay LM5100A/B/C LI Rising to LO Rising 20 45 ns
LO turnon propagation delay LM5101A/B/C 26 56 ns
tHPHL HO turnoff propagation delay LM5100A/B/C HI Falling to HO Falling 20 45 ns
HO turnoff propagation delay LM5101A/B/C 22 56 ns
tHPLH LO turnon propagation delay LM5100A/B/C HI Rising to HO Rising 20 45 ns
LO turnon propagation delay LM5101A/B/C 26 56 ns
tMON Delay matching: LO on and HO off LM5100A/B/C 1 10 ns
Delay matching: LO on and HO off LM5101A/B/C 4 10 ns
tMOFF Delay matching: LO off and HO on LM5100A/B/C 1 10 ns
Delay matching: LO on and HO off LM5101A/B/C 4 10 ns
tRC, tFC Either output rise and fall time CL = 1000 pF 8 ns
tR Output rise time (3 V to 9 V) LM5100A/LM5101A CL = 0.1 µF 430 ns
Output rise time (3 V to 9 V) LM5100B/LM5101B 570 ns
Output rise time (3 V to 9 V) LM5100C/LM5101C 990 ns
tF Output fall time (3 V to 9 V) LM5100A/LM5101A CL = 0.1 µF 260 ns
Output fall time (3 V to 9 V) LM5100B/LM5101B 430 ns
Output fall time (3 V to 9 V) LM5100C/LM5101C 715 ns
tPW Minimum input pulse width that changes the output 50 ns
tBS Bootstrap diode reverse recovery time IF = 100 mA,
IR = 100 mA 		37 ns
(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203104.gif Figure 1. Timing Diagram

7.7 Typical Characteristics

LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203127.gif Figure 2. Peak Sourcing Current vs VDD
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203129.gif Figure 4. Sink Current vs Output Voltage
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203109.gif Figure 6. LM5100A/B/C IDD vs Frequency
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203111.gif Figure 8. Operating Current vs Temperature
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203118.gif Figure 10. Quiescent Current vs Supply Voltage
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203122.gif Figure 12. Undervoltage Rising Thresholds vs Temperature
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203115.gif Figure 14. Bootstrap Diode Forward Voltage
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203124.gif Figure 16. LM5101A/B/C Input Threshold vs Temperature
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203126.gif Figure 18. LM5101A/B/C Input Threshold vs VDD
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203113.gif Figure 20. LM5101A/B/C Propagation Delay vs Temperature
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203121.gif Figure 22. LO and HO Gate Drive - Low Level Output Voltage vs Temperature
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203132.gif Figure 24. LO and HO Gate Drive - Output Low Voltage vs VDD
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203128.gif Figure 3. Peak Sinking Current vs VDD
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203130.gif Figure 5. Source Current vs Output Voltage
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203110.gif Figure 7. LM5101A/B/C IDD vs Frequency
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203114.gif Figure 9. IHB vs Frequency
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203119.gif Figure 11. Quiescent Current vs Temperature
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203117.gif Figure 13. Undervoltage Threshold Hysteresis vs Temperature
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203123.gif Figure 15. LM5100A/B/C Input Threshold vs Temperature
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203125.gif Figure 17. LM5100A/B/C Input Threshold vs VDD
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203112.gif Figure 19. LM5100A/B/C Propagation Delay vs Temperature
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203120.gif Figure 21. LO and HO Gate Drive - High Level Output Voltage vs Temperature
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203131.gif Figure 23. LO and HO Gate Drive - Output High Voltage vs VDD