SNOSAW2Q September   2006  – November 2015 LM5100A , LM5100B , LM5100C , LM5101A , LM5101B , LM5101C

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Start-up and UVLO
      2. 8.3.2 Level Shift
      3. 8.3.3 Bootstrap Diode
      4. 8.3.4 Output Stages
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Select Bootstrap and VDD capacitor
        2. 9.2.2.2 Select External Bootstrap Diode and Resistor
        3. 9.2.2.3 Select Gate driver Resistor
        4. 9.2.2.4 Estimate the Driver Power Losses
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

D Package
8-Pin SOIC
Top View
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203101.gif
NGT Package
8-Pin WSON With Exposed Thermal Pad
Top View
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203137.gif
DPR Package
10-Pin WSON With Exposed Thermal Pad
Top View
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203102.gif
DDA Package
8-Pin SO PowerPAD
Top View
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203135.gif
DGN Package
8-Pin MSOP-PowerPAD
Top View
LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 20203136.gif

Pin Functions

PIN I/O DESCRIPTION
NAME 8 PINS 10 PINS(1)
HB 2 2 I High-side gate driver bootstrap supply. Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be placed as close to the IC as possible.
HI 5 7 I High-side driver control input. The LM5100A/B/C inputs have CMOS type thresholds. The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open.
HO 3 3 O High-side gate driver output. Connect to the gate of high-side MOSFET with a short, low inductance path.
HS 4 4 — High-side MOSFET source connection. Connect to the bootstrap capacitor negative terminal and the source of the high-side MOSFET.
LI 6 8 I Low-side driver control input. The LM5100A/B/C inputs have CMOS type thresholds. The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open.
LO 8 10 O Low-side gate driver output. Connect to the gate of the low-side MOSFET with a short, low inductance path.
VDD 1 1 I Positive gate drive supply . Locally decouple to VSS using low ESR/ESL capacitor located as close to the IC as possible.
VSS 7 9 — Ground return. All signals are referenced to this ground.
EP(2) — TI recommends that the exposed pad on the bottom of the package is soldered to ground plane on the PC board, and that ground plane should extend out from beneath the IC to help dissipate heat.
(1) For WSON-10 package, pins 5 and 6 have no connection.
(2) Exposed pad is not available on the 8-pin SOIC package.