JAJSC49E February   2005  – August 2016 LM5105

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Dissipation Considerations
    2. 9.2 HS Transient Voltages Below Ground
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Detailed Description

7.1 Overview

The LM5105 is a single PWM input Gate Driver with Enable that offers a programmable dead time. The dead time is set with a resistor at the RDT pin and can be adjusted from 100 ns to 600 ns. The wide dead-time programming range provides the flexibility to optimize drive signal timing for a wide range of MOSFETS and applications.

The RDT pin is biased at 3 V and current-limited to 1-mA maximum programming current. The time delay generator accommodates resistor values from 5 k to 100 k with a dead time that is proportional to the RDT resistance. Grounding the RDT pin programs the LM5105 to drive both outputs with minimum dead time.

7.2 Functional Block Diagram

LM5105 20137502.gif

7.3 Feature Description

7.3.1 Start-Up and UVLO

Both top and bottom drivers include undervoltage lockout (UVLO) protection circuitry, which monitors the supply voltage (VDD) and bootstrap capacitor voltage (HB – HS) independently. The UVLO circuit inhibits each driver until sufficient supply voltage is available to turn on the external MOSFETs, and the UVLO hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to the VDD pin of LM5105, the top and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.9 V. Any UVLO condition on the bootstrap capacitor disables only the high-side output (HO).

7.4 Device Functional Modes

Table 1 lists the functional modes for LM5105.

Table 1. Function Table

EN IN PIN LO PIN HO PIN
L Any L L
H H L H
H L H L