JAJSHD4 データシート | TI.com

JAJSHD4A may 2019 – july 2023 LM5108

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

DRC|10
- MPDS117L

サーマルパッド・メカニカル・データ

DRC|10
- QFND013N

発注情報

6.7 Typical Characteristics

Unless otherwise specified V_VDD=V_HB = 12 V, V_HS=V_VSS = 0 V, No load on outputs

V_HI = V_LI = 0 V

Figure 6-2 VDD Quiescent Current

C_L = 0 F

V_DD =V_HB= 12V

Figure 6-4 VDD Operating Current

C_L = 0 F

V_EN = 0 V

Figure 6-6 VDD Current When Disabled

Figure 6-8 Input Falling Threshold

Figure 6-10 Enable Threshold

Figure 6-12 VDD UVLO Threshold

Figure 6-14 Boot Diode Forward Voltage Drop

C_L=1000pF

Figure 6-16 LO Rise Time

C_L=1000pF

Figure 6-18 HO Rise Time

C_L=No Load

Figure 6-20 HO Rising Propagation Delay (TDHRR)

C_L= No Load

Figure 6-22 LO Rising Propagation Delay (TDLRR)

V_HI = V_LI = 0 V

Figure 6-3 HB Quiescent Current

C_L = 0 F

V_DD =V_HB= 12V

Figure 6-5 HB Operating Current

Figure 6-7 Input Rising Threshold

Figure 6-9 Input Pull-down Resistor

Figure 6-11 Disable Threshold

Figure 6-13 HB UVLO Threshold

Figure 6-15 Boot Diode Dynamic Resistance

C_L=1000pF

Figure 6-17 LO Fall Time

C_L=1000pF

Figure 6-19 HO Fall Time

C_L= No Load

Figure 6-21 HO Falling Propagation Delay (TDHFF)

C_L= No Load

Figure 6-23 LO Falling Propagation Delay (TDLFF)