JAJSHD4A may   2019  – july 2023 LM5108

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Input Stages and Interlock Protection
      4. 7.3.4 Level Shifter
      5. 7.3.5 Output Stage
      6. 7.3.6 Negative Voltage Transients
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 Estimate Driver Power Losses
        3. 8.2.2.3 Selecting External Gate Resistor
        4. 8.2.2.4 Delays and Pulse Width
        5. 8.2.2.5 External Bootstrap Diode
        6. 8.2.2.6 VDD and Input Filter
        7. 8.2.2.7 Transient Protection
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Switching Characteristics

VDD = VHB = VEN = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = 25°C, (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
PROPAGATION DELAYS
tDLFFVLI falling to VLO fallingSee Figure 6-120ns
tDHFFVHI falling to VHO fallingSee Figure 6-120ns
tDLRRVLI rising to VLO risingSee Figure 6-120ns
tDHRRVHI rising to VHO risingSee Figure 6-120ns
DELAY MATCHING
tMONFrom LO being ON to HO being OFFSee Figure 6-115ns
tMOFFFrom LO being OFF to HO being ONSee Figure 6-115ns
OUTPUT RISE AND FALL TIME
tRLO, HO rise timeCLOAD = 1000 pF11ns
tFLO, HO fall timeCLOAD = 1000 pF8ns
MISCELLANEOUS
TPW,minMinimum input pulse width that changes the output40ns
Bootstrap diode turnoff timeIF = 20 mA, IREV = 0.5 A20ns
GUID-7404CD8C-07CC-4D1E-A6AF-8581D4521699-low.gifFigure 6-1 Timing Diagram