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LM5112デバイスはMOSFETゲート・ドライバで、高いピーク・ゲート・ドライブ電流を供給し、小型の6ピンWSONパッケージ(SOT-23と同等の占有面積)または8ピンの露出パッド付きMSOPパッケージに搭載され、高い周波数での動作に必要な消費電力の改善が加えられています。複合出力ドライバのステージではMOSとバイポーラ・トランジスタが並列で動作し、容量性負荷から7Aを超えるピーク電流をシンクします。MOSとバイポーラ・デバイスの固有の特性を組み合わせることで、電圧および温度による駆動電流の変動が低減されます。低電圧誤動作防止保護が実装され、ゲートのターンオン電圧の不足によるMOSFETの損傷を防ぎます。LM5112デバイスには反転と非反転の両方の入力があり、単一のデバイス・タイプで反転と非反転のゲート・ドライブの要件を満たすことができます。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
LM5112、 LM5112-Q1 |
WSON (6) | 3.00mm×3.00mm |
MSOP PowerPAD (8) | 3.00mm×3.00mm |
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | WSON | MSOP | |||
Exposed Pad | — | — | — | Exposed pad, underside of package: Internally bonded to the die substrate. Connect to VEE ground pin for low thermal impedance. | |
IN | 1 | 4 | I | Non-inverting input pin: TTL compatible thresholds. Pull up to VCC when not used. | |
INB | 6 | 2 | I | Inverting input pin: TTL compatible thresholds. Connect to IN_REF when not used. | |
IN_REF | 5 | 1 | — | Ground reference for control inputs: Connect to power ground (VEE) for standard positive only output voltage swing. Connect to system logic ground when VEE is connected to a negative gate drive supply. | |
N/C | — | 5, 8 | — | Not internally connected | |
OUT | 4 | 7 | O | Gate drive output: Capable of sourcing 3 A and sinking 7 A. Voltage swing of this output is from VEE to VCC. | |
VCC | 3 | 6 | I | Positive supply voltage input: Locally decouple to VEE. The decoupling capacitor must be placed close to the chip. | |
VEE | 2 | 3 | — | Power ground for driver outputs: Connect to either power ground or a negative gate drive supply for positive or negative voltage swing. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC to VEE | –0.3 | 15 | V | |
VCC to IN_REF | –0.3 | 15 | V | |
IN/INB to IN_REF | –0.3 | 15 | V | |
IN_REF to VEE | –0.3 | 5 | V | |
Maximum junction temperature | 150 | °C | ||
Operating junction temperature | –40 | 125 | °C | |
Storage temperature, Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Operating voltage, VCC – IN_REF and VCC – VEE | 3.5 | 14 | V | |
Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | LM5112, LM5112-Q1 | UNIT | ||
---|---|---|---|---|
NGG (WSON) | DGN (MSOP PowerPAD) | |||
6 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 40 | 53.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 50.8 | 61.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 29.3 | 37.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.7 | 7.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 29.5 | 36.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 7.5 | 4.7 | °C/W |
PARAMETER | CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY | ||||||
VCC | Operating voltage | VCC – IN_REF and VCC – VEE | 3.5 | 14 | V | |
UVLO | Undervoltage lockout (rising) | VCC – IN_REF | 2.4 | 3 | 3.5 | V |
VCCH | Undervoltage hysteresis | 230 | mV | |||
ICC | Supply current | 1 | 2 | mA | ||
CONTROL INPUTS | ||||||
VIH | Logic high | 2.3 | V | |||
VIL | Logic low | 0.8 | V | |||
VthH | High threshold | 1.3 | 1.75 | 2.3 | V | |
VthL | Low threshold | 0.8 | 1.35 | 2 | V | |
HYS | Input hysteresis | 400 | mV | |||
IIL | Input current low | IN = INB = 0 V | –1 | 0.1 | 1 | µA |
IIH | Input current high | IN = INB = VCC | –1 | 0.1 | 1 | µA |
OUTPUT DRIVER | ||||||
ROH | Output resistance high | IOUT = –10 mA(1) | 30 | 50 | Ω | |
ROL | Output resistance low | IOUT = 10 mA(1) | 1.4 | 2.5 | Ω | |
ISOURCE | Peak source current | OUT = VCC / 2,200 ns pulsed current | 3 | A | ||
ISINK | Peak sink current | OUT = VCC / 2,200 ns pulsed current | 7 | A | ||
LATCHUP PROTECTION | ||||||
AEC–Q100, METHOD 004 | TJ = 150°C | 500 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
td1 | Propagation delay time low to high, IN or INB rising (IN to OUT) |
CLOAD = 2 nF, see Figure 13 | 25 | 40 | ns | |
td2 | Propagation delay time high to low, IN or INB falling (IN to OUT) |
CLOAD = 2 nF, see Figure 13 | 25 | 40 | ns | |
tr | Rise time | CLOAD = 2 nF, see Figure 13 | 14 | ns | ||
tf | Fall time | CLOAD = 2 nF, see Figure 13 | 12 | ns |
The LM5112 device is a high-speed, high-peak current (7 A) single-channel MOSFET driver. The high-peak output current of the LM5112 device switches power MOSFETs on and off with short rise and fall times, thereby reducing switching losses considerably. The LM5112 device includes both inverting and non-inverting inputs that give the user flexibility to drive the MOSFET with either active low or active high logic signals. The driver output stage consists of a compound structure with MOS and bipolar transistor operating in parallel to optimize current capability over a wide output voltage and operating temperature range. The bipolar device provides high peak current at the critical Miller plateau region of the MOSFET VGS, while the MOS device provides rail-to-rail output swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage VCC and the power ground potential at the VEE pin.
The control inputs of the driver are high impedance CMOS buffers with TTL compatible threshold voltages. The negative supply of the input buffer is connected to the input ground pin IN_REF. An internal level shifting circuit connects the logic input buffers to the totem pole output drivers. The level shift circuit and the separate input or output ground pins provide the option of single supply or split supply configurations. When driving the MOSFET gate from a single positive supply, the IN_REF and VEE pins are both connected to the power ground.
The isolated input and output stage grounds provide the capability to drive the MOSFET to a negative VGS voltage for a more robust and reliable off state. In split supply configuration, the IN_REF pin is connected to the ground of the controller which drives the LM5112 inputs. The VEE pin is connected to a negative bias supply that can range from the IN_REF potential to as low as 14 V below the VCC gate drive supply. For reliable operation, the maximum voltage difference between VCC and IN_REF or between VCC and VEE is 14 V.
The minimum recommended operating voltage between VCC and IN_REF is 3.5 V. An undervoltage lockout (UVLO) circuit is included in the LM5112 which senses the voltage difference between VCC and the input ground pin, IN_REF. When the VCC to IN_REF voltage difference falls below 2.8 V the driver is disabled and the output pin is held in the low state. The UVLO hysteresis prevents chattering during brown-out conditions; the driver resumes normal operation when the VCC to IN_REF differential voltage exceeds 3 V.
The device output state is dependent on states of the IN and INB pins. Table 1 lists the output states for different input pin combinations.
IN PIN | INB PIN | OUT PIN |
---|---|---|
L | L | L |
L | H | L |
H | L | H |
H | H | L |
During the inverting mode of operation, INB is used as the control input and the polarity of OUT is reversed with respect to INB. Figure 12 shows a timing diagram of this mode. The IN pin is not used in this mode of operation and must be pulled up to VCC.
During the non-inverting mode of operation, IN is used as the control input and the polarity of OUT is the same with respect to IN. Figure 13 shows a timing diagram of this mode. The INB pin is not used in this mode of operation and must be connected to IN_REF.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
A leading application for gate drivers such as the LM5112 is providing a high power buffer stage between the PWM output of a control IC and the gates of the primary power switching devices. In other cases, the driver IC is used to drive the power device gates through a drive transformer. Driver ICs are used when it is not feasible to have the primary PWM regulator IC directly drive the switching devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application.
The LM5112 is used to drive a low side MOSFET with low switching losses. Either one of the control input pins, IN or INB, are used to control the gate drive to the MOSFET. The choice of the control input pin used depends on the polarity of operation.
Typical application diagrams for the LM5112 device are shown below, illustrating use in non-inverting and inverting driver configurations. The high peak gate drive current of the LM5112 allows for short rise and fall times on the low-side MOSFET, thereby improving overall efficiency of the system and reducing switching losses.
When selecting the proper gate driver device for an end application, some design considerations must be evaluated first to make the most appropriate selection. Among these considerations are input-to-output configuration, the input threshold type, bias supply voltage levels, peak source and sink currents, capacitive load, and switching frequency. Table 2 shows some sample values for a typical application.
PARAMETER | VALUE |
---|---|
Input-to-output logic | Non-inverting |
VCC bias supply voltage (measured with respect to VEE) |
12 V |
Supply configuration | Split supply |
Peak source current | 3 A |
Peak sink current | 7 A |
Output load (MOSFET gate capacitance) | 2 nF |
Gate drive resistor | 1 Ω |
Switching frequency | 300 kHz |
See Power Supply Recommendations, Layout, and Thermal Considerations for key design considerations regarding the input supply, grounding, and thermal calculations specific to the LM5112.
The rise and fall times of the OUT signal depends on the capacitance of the MOSFET gate. Therefore, an appropriate MOSFET must be selected to meet the switching speed and efficiency requirements of the system. Figure 16 shows the rise and fall time curves as a function of capacitive load. Figure 17 shows output rise and fall time measured on an application board, showing actual device performance. The testing conditions for this figure are Cload= 2.2 nF, Rdrive = 1 Ω, and fs = 300 kHz.