JAJSC47I June   2011  – October 2019 LM5113

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and Output
      2. 8.3.2 Start-Up and UVLO
      3. 8.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
      4. 8.3.4 Level Shift
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VDD Bypass Capacitor
        2. 9.2.2.2 Bootstrap Capacitor
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 サポート・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.2 Start-Up and UVLO

The start-up voltage sequencing for this device is as follows: VDD voltage first, with the VIN voltage present thereafter.

The LM5113 requires an external bootstrap diode with a 20-Ω series resistor to charge the high-side supply on a cycle-by-cycle basis. The recommended bootstrap diode options are BAT46, BAT41, or LL4148.

The LM5113 has an Undervoltage Lockout (UVLO) on both the VDD and bootstrap supplies. When the VDD voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs from being partially turned on. Also if there is insufficient VDD voltage, the UVLO will actively pull the LOL and HOL low. When the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only HOL is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering.

Table 1. VDD UVLO Feature Logic Operation

CONDITION (VHB-HS > VHBR for all cases below) HI LI HO LO
VDD - VSS < VDDR during device start-up H L L L
VDD - VSS < VDDR during device start-up L H L L
VDD - VSS < VDDR during device start-up H H L L
VDD - VSS < VDDR during device start-up L L L L
VDD - VSS < VDDR - VDDH after device start-up H L L L
VDD - VSS < VDDR - VDDH after device start-up L H L L
VDD - VSS < VDDR - VDDH after device start-up H H L L
VDD - VSS < VDDR - VDDH after device start-up L L L L

Table 2. VHB-HS UVLO Feature Logic Operation

CONDITION (VDD > VDDR for all cases below) HI LI HO LO
VHB-HS < VHBR during device start-up H L L L
VHB-HS < VHBR during device start-up L H L H
VHB-HS < VHBR during device start-up H H L H
VHB-HS < VHBR during device start-up L L L L
VHB-HS < VHBR - VHBH after device start-up H L L L
VHB-HS < VHBR - VHBH after device start-up L H L H
VHB-HS < VHBR - VHBH after device start-up H H L H
VHB-HS < VHBR - VHBH after device start-up L L L L