A voltage divider and filter can be connected to the UVLO pin to set a minimum operating voltage V_IN(MIN) for the regulator. If this feature is required, the following procedure can be used to determine appropriate resistor values for R_UV2, R_UV1 and C_FT.

1. R_UV2 must be large enough such that in the event of a current limit, the internal UVLO switch can pull UVLO < 200 mV. This can be accomplished if: R_UV2 > 500 ✕ V_IN(MAX)Where V_IN(MAX) is the maximum input voltage and R_UV2 is in ohms.
2. With an appropriate value for R_UV2, R_UV1 can be selected using the following equation:
   
   Where V_IN(MIN) is the desired shutdown voltage.
3. Capacitor C_FT provides filtering for the divider and determines the off-time of the “hiccup” duty cycle during current limit. When C_FT is used in conjunction with the voltage divider, a diode across the top resistor must be used to discharge C_FT in the event of an input undervoltage condition.
   

If undervoltage shutdown is not required, R_UV1 and R_UV2 can be eliminated and the off-time becomes:

Equation 25.

The voltage at the UVLO pin must never exceed 16 V when using an external set-point divider. It can be necessary to clamp the UVLO pin at high input voltages. For the design example, R_UV2 = 102 kΩ and R_UV1 = 21 kΩ for a shut-down voltage of 6.6 V. If sustained short circuit protection is required, C_FT ≥ 1 µF will limit the short circuit power dissipation. D2 can be installed when using C_FT with R_UV1 and R_UV2.