JAJSRS8I February   2007  – November 2023 LM5116

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Performance Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High Voltage Start-Up Regulator
      2. 6.3.2 Enable
      3. 6.3.3 UVLO
      4. 6.3.4 Oscillator and Sync Capability
      5. 6.3.5 Error Amplifier and PWM Comparator
      6. 6.3.6 Ramp Generator
      7. 6.3.7 Current Limit
      8. 6.3.8 HO Output
      9. 6.3.9 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Soft-Start and Diode Emulation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design with WEBENCH® Tools
        2. 7.2.2.2  Timing Resistor
        3. 7.2.2.3  Output Inductor
        4. 7.2.2.4  Current Sense Resistor
        5. 7.2.2.5  Ramp Capacitor
        6. 7.2.2.6  Output Capacitors
        7. 7.2.2.7  Input Capacitors
        8. 7.2.2.8  VCC Capacitor
        9. 7.2.2.9  Bootstrap Capacitor
        10. 7.2.2.10 Soft Start Capacitor
        11. 7.2.2.11 Output Voltage Divider
        12. 7.2.2.12 UVLO Divider
        13. 7.2.2.13 MOSFETs
        14. 7.2.2.14 MOSFET Snubber
        15. 7.2.2.15 Error Amplifier Compensation
        16. 7.2.2.16 Comprehensive Equations
          1. 7.2.2.16.1 Current Sense Resistor and Ramp Capacitor
          2. 7.2.2.16.2 Modulator Transfer Function
          3. 7.2.2.16.3 Error Amplifier Transfer Function
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design with WEBENCH® Tools
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
7.2.2.16.1 Current Sense Resistor and Ramp Capacitor

T = 1 / fSW, gm = 5 µA/V, A = 10 V/V. IOUT is the maximum output current at current limit.

General Method for VOUT < 5 V:

Equation 33. GUID-694C1969-6570-43E0-9887-D120FAF5723E-low.gif
Equation 34. GUID-ABCC0316-014E-479C-9505-83241C232507-low.gif

General Method for 5 V < VOUT < 7.5 V:

Equation 35. GUID-390B1DF1-49DD-43B4-A533-7F3D4D599A79-low.gif
Equation 36. GUID-AAE10ABD-E5A6-4397-B506-ABCA343D37B8-low.gif

Best Performance Method:

This minimizes the current limit deviation due to changes in line voltage, while maintaining near optimal slope compensation.

Calculate optimal slope current, IOS = (VOUT / 3) ✕ 10 µA/V. For example, at VOUT = 7.5 V, IOS = 25 µA.

Equation 37. GUID-6F2D4AA5-9FFF-431A-983C-9873A9F9F223-low.gif

Calculate VRAMP at the nominal input voltage.

Equation 38. GUID-3FC65E16-D435-4153-996A-48999962DB71-low.gif

For VOUT > 7.5 V, install a resistor from the RAMP pin to VCC.

Equation 39. GUID-AB40A9B0-FEB6-4713-92C9-44AE8C6C2820-low.gif
GUID-A9D4B399-059A-4AE8-8DF8-3790249155EE-low.gif Figure 7-6 RRAMP to VCC for VOUT > 7.5 V

For VOUT < 7.5 V, a negative VCC is required. This can be made with a simple charge pump from the LO gate output. Install a resistor from the RAMP pin to the negative VCC.

Equation 40. GUID-E57B1C3A-27D5-4F39-8B66-D11B672481FC-low.gif
GUID-80DC3A56-0FA4-4E52-B4C9-48647D20E233-low.gif Figure 7-7 RRAMP to -VCC for VOUT < 7.5 V

If a large variation is expected in VCC, say for VIN < 11 V, a Zener regulator can be added to supply a constant voltage for RRAMP.