JAJSRS8I February   2007  – November 2023 LM5116

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Performance Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High Voltage Start-Up Regulator
      2. 6.3.2 Enable
      3. 6.3.3 UVLO
      4. 6.3.4 Oscillator and Sync Capability
      5. 6.3.5 Error Amplifier and PWM Comparator
      6. 6.3.6 Ramp Generator
      7. 6.3.7 Current Limit
      8. 6.3.8 HO Output
      9. 6.3.9 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Soft-Start and Diode Emulation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design with WEBENCH® Tools
        2. 7.2.2.2  Timing Resistor
        3. 7.2.2.3  Output Inductor
        4. 7.2.2.4  Current Sense Resistor
        5. 7.2.2.5  Ramp Capacitor
        6. 7.2.2.6  Output Capacitors
        7. 7.2.2.7  Input Capacitors
        8. 7.2.2.8  VCC Capacitor
        9. 7.2.2.9  Bootstrap Capacitor
        10. 7.2.2.10 Soft Start Capacitor
        11. 7.2.2.11 Output Voltage Divider
        12. 7.2.2.12 UVLO Divider
        13. 7.2.2.13 MOSFETs
        14. 7.2.2.14 MOSFET Snubber
        15. 7.2.2.15 Error Amplifier Compensation
        16. 7.2.2.16 Comprehensive Equations
          1. 7.2.2.16.1 Current Sense Resistor and Ramp Capacitor
          2. 7.2.2.16.2 Modulator Transfer Function
          3. 7.2.2.16.3 Error Amplifier Transfer Function
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design with WEBENCH® Tools
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-3F64236D-558A-4EF3-84CF-CDC0AA67B49C-low.gif Figure 4-1 PWP Package, 20-Pin HTSSOP Top View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 6 G Analog ground. Connect to PGND through the exposed pad ground connection under the LM5116.
COMP 9 O Output of the internal error amplifier. The loop compensation network must be connected between this pin and the FB pin.
CS 12 I Current sense amplifier input. Connect to the top of the current sense resistor or the drain of the low-sided MOSFET if RDS(ON) current sensing is used.
CSG 13 G Current sense amplifier input. Connect to the bottom of the sense resistor or the source of the low-side MOSFET if RDS(ON) current sensing is used.
DEMB 11 I Low-side MOSFET source voltage monitor for diode emulation. For start-up into a pre-biased load, tie this pin to ground at the CSG connection. For fully synchronous operation, use an external series resistor between DEMB and ground to raise the diode emulation threshold above the low-side SW on-voltage.
EN 4 I If the EN pin is below 0.5 V, the regulator is in a low-power state, drawing less than 10 µA from VIN. EN must be pulled above 3.3 V for normal operation. The maximum EN transition time for proper operation is one switching period.
FB 8 I Feedback signal from the regulated output. This pin is connected to the inverting input of the internal error amplifier. The regulation threshold is 1.215 V.
HB 18 P High-side driver supply for bootstrap gate drive. Connect to the cathode of the bootstrap diode and the positive terminal of the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side MOSFET gate and must be placed as close to the controller as possible.
HO 19 O Connect to the gate of the high-side synchronous MOSFET through a short, low inductance path
LO 15 O Connect to the gate of the low-side synchronous MOSFET through a short, low inductance path.
PGND 14 G Power ground. Connect to AGND through the exposed pad ground connection under the LM5116
RAMP 5 I Ramp control signal. An external capacitor connected between this pin and the AGND pin sets the ramp slope used for current mode control.
RT/SYNC 3 I The internal oscillator is set with a single resistor between this pin and the AGND pin. The recommended frequency range is 50 kHz to 1 MHz. The internal oscillator can be synchronized to an external clock by AC coupling a positive edge onto this node.
SS 7 I An external capacitor and an internal 10-µA current source set the soft start time constant for the rise of the error amp reference. The SS pin is held low during VCC < 4.5 V, UVLO < 1.215 V, EN input low, or thermal shutdown.
SW 20 O Switch node. Connect to the negative terminal of the bootstrap capacitor and the source terminal of the high-side MOSFET.
VIN 1 P Chip supply voltage, input voltage monitor, and input to the VCC regulator.
UVLO 2 I If the UVLO pin is below 1.215 V, the regulator is in standby mode (VCC regulator running, switching regulator disabled). If the UVLO pin voltage is above 1.215 V, the regulator is operational. An external voltage divider can set an undervoltage shutdown threshold. There is a fixed 5-µA pullup current on this pin when EN is high. UVLO is pulled to ground when a current limit condition exists for 256 clock cycles.
VCC 16 P Locally decouple to PGND using a low ESR/ESL capacitor located as close to the controller as possible.
VCCX 17 P Optional input for an externally supplied VCC. If VCCX > 4.5 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. If VCCX is unused, VCCX must be connected to ground.
VOUT 10 I Output monitor. Connect directly to the output voltage.
EP EP — Exposed pad. Solder to ground plane.
(1) G = Ground, I = Input, O = Output, P = Power