JAJSNE2 October   2022 LM51231-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Enable/Disable (EN, VH Pin)
      2. 7.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 7.3.3  Light Load Switching Mode Selection (MODE Pin)
      4. 7.3.4  VOUT Range Selection (RANGE Pin)
      5. 7.3.5  Line Undervoltage Lockout (UVLO Pin)
      6. 7.3.6  Fast Restart using VCC HOLD (VH Pin)
      7. 7.3.7  Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
      8. 7.3.8  Overvoltage Protection (VOUT Pin)
      9. 7.3.9  Power Good Indicator (PGOOD Pin)
      10. 7.3.10 Dynamically Programmable Switching Frequency (RT)
      11. 7.3.11 External Clock Synchronization (SYNC Pin)
      12. 7.3.12 Programmable Spread Spectrum (DITHER Pin)
      13. 7.3.13 Programmable Soft-start (SS Pin)
      14. 7.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
      15. 7.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
      16. 7.3.16 Constant Peak Current Limit (CSP, CSN Pin)
      17. 7.3.17 Maximum Duty Cycle and Minimum Controllable On-time Limits
      18. 7.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
      19. 7.3.19 Thermal Shutdown Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Status
        1. 7.4.1.1 Shutdown Mode
        2. 7.4.1.2 Configuration Mode
        3. 7.4.1.3 Active Mode
        4. 7.4.1.4 Bypass Mode
          1. 7.4.1.4.1 Bypass DE mode
          2. 7.4.1.4.2 Bypass FPWM
      2. 7.4.2 Light Load Switching Mode
        1. 7.4.2.1 Forced PWM (FPWM) Mode
        2. 7.4.2.2 Diode Emulation (DE) Mode
        3. 7.4.2.3 Forced Diode Emulation Operation in FPWM Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Ideas
      4. 8.2.4 Application Curves
    3. 8.3 System Example
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
7.4.1.4.2 Bypass FPWM

In FPWM switching operation, the device enters bypass mode when the OVP status is triggered for at least 30 μs (VOVTH-DLY) and VCSP-CSN is greater than 6 mV (VCS-FWD), indicating positive inductor current. To exit bypass mode the either the OVP status is cleared or VSW-SENSE is less than -150 mV (VI-NEG-BYP). Current flow from VLOAD to VSUPPLY can occur in bypass mode while operating in FPWM. Once the high-side FET is disabled, the device enters active mode. The proper conditions must be achieved to enter bypass mode again. See Table 7-2 for details on how the device enters and exits bypass mode.

Table 7-2 Bypass Mode: FPWM
Conditions (1)
Enter bypass mode VVOUT >VTRK *KFB*VOVTH_RISING
AND
VCSP-CSN > VCS-FWD
Exit bypass mode VVOUT < VTRK *KFB*VOVTH_FALLING
OR
VSW-SENSE < VI-NEG-BYP
(1) KFB is either 20 or 60 depending on the selected output voltage range. See section Section 7.3.7