SLVSES8A October   2020  – December 2020 LM5127-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Enable (EN, VCC_HOLD)
      2. 8.3.2  Dual Input VCC Regulator (BIAS, VCCX, VCC)
      3. 8.3.3  Dual Input VDD Switch (VDD, VDDX)
      4. 8.3.4  Device Configuration and Light Load Switching Mode Selection (CFG/MODE)
      5. 8.3.5  Fixed or Adjustable Output Regulation Target (VOUT, FB)
      6. 8.3.6  Overvoltage Protection (VOUT, FB)
      7. 8.3.7  Power Good Indicator (PGOOD)
      8. 8.3.8  Programmable Switching Frequency (RT)
      9. 8.3.9  External Clock Synchronization (SYNC)
      10. 8.3.10 Programmable Spread Spectrum (DITHER)
      11. 8.3.11 Programmable Soft Start (SS)
      12. 8.3.12 Fast Re-start using VCC_HOLD (VCC_HOLD)
      13. 8.3.13 Transconductance Error Amplifier and PWM (COMP)
      14. 8.3.14 Current Sensing and Slope Compensation (CSA, CSB)
      15. 8.3.15 Constant Peak Current Limit (CSA, CSB)
      16. 8.3.16 Maximum Duty Cycle and Minimum Controllable On-time Limits (Boost)
      17. 8.3.17 Bypass Mode (Boost)
      18. 8.3.18 Minimum Controllable On-time and Minimum Controllable Off-time Limits (Buck)
      19. 8.3.19 Low Dropout Mode for Extended Minimum Input Voltage (Buck)
      20. 8.3.20 Programmable Hiccup Mode Overload Protection (RES)
      21. 8.3.21 MOSFET Drivers and Hiccup Mode Fault Protection (LO, HO, HB)
      22. 8.3.22 Battery Monitor (BMOUT, BMIN_FIX, BMIN_PRG)
      23. 8.3.23 Dual-phase Interleaved Configuration for High Current Supply (CFG)
      24. 8.3.24 Thermal Shutdown Protection
      25. 8.3.25 External VCCX Supply Reduces Power Dissipation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Status
        1. 8.4.1.1 Shutdown Mode
        2. 8.4.1.2 Configuration Mode
        3. 8.4.1.3 Active Mode
        4. 8.4.1.4 Sleep Mode
        5. 8.4.1.5 Deep Sleep Mode
          1. 8.4.1.5.1 Cutting Leakage Path in Deep Sleep Mode (DIS, SLEEP1, SENSE1)
        6. 8.4.1.6 VCC HOLD Mode
      2. 8.4.2 Light Load Switching Mode
        1. 8.4.2.1 Forced PWM (FPWM) Operation
        2. 8.4.2.2 Diode Emulation (DE) Operation (Connect RSS at SS)
        3. 8.4.2.3 Forced Diode Emulation Operation in FPWM Mode
        4. 8.4.2.4 Skip Mode Operation
      3. 8.4.3 LM5127 Cheat Sheet
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Recommended Power Tree Architecture
        2. 9.2.2.2 Application Ideas
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1.6 VCC HOLD Mode

After the initial configuration is finished, the device enters the VCC HOLD mode if all EN pins are less than VEN and VCC_HOLD is greater than VSYNC. During the VCC_HOLD mode, VCC and VDD are maintained and the battery monitor is enabled if buck configuration. The VCC_HOLD mode is useful when the device needs to restart fast without the initial configuration time delay.

Table 8-9 Pin Status in Steady State #1 (When BIAS > ~ 5.5 V)
SHUTDOWNCONFIGURATIONACTIVE (CHANNEL BASE)SLEEP (CHANNEL BASE)DEEP SLEEPVCC HOLD
ENAll EN pins < 0.4 VAt least one pin > 2.0 VAt least one pin > 2.0 VAll EN pins < 0.4 V
VCC_HOLD /SYNC /DITHER< 0.4 VSYNC/DITHER enabledSYNC/DITHER disabled> 2.0 V
CFG/MODEDisabledEnabledDisabled
BIASIQ < 3 μAIQ < 150 μAIQ = 1.3 mA - 3.0 mANot specifiedIQ= ~2 μAIQ < 25 μA
VCCDischargedVCC regulator is enabledVCC regulator is enabled if VCCX is not in use.Active with 1-mA current limit if VCCX is not in use.
VCC-VCCX switchOpen with diode pathClosed if VCCX > 4.4 V
VCC-VDD switchOpenClosed if at least one channel is activeClosed if VDDX is not in use.Closed
VDDX-VDD switchOpenClosed if at least one channel is activeClosed if VDDX use (VOUT3 = Fixed 3.3 V)Open
RTDisabledEnabledDisabled
RESDisabledRES mode detectionEnabled if at least one channel is activeDisabled
SENSE1 (Boost)DisabledEnabledDisabled
SLEEP1 (Boost)DisabledEnabledDisabled
DIS switch (Boost)OpenGNDOpen
BMIN_FIX (Buck)DisabledActive if at least one channel is activeEnabled
BMIN_PRG (Buck)Disabled
BMOUT switch (Buck)Open
Table 8-10 Pin Status in Steady State #2 (When BIAS > 5.5 V)
SHUTDOWNCONFIGURATIONACTIVE (CHANNEL BASE)SLEEP (CHANNEL BASE)DEEP SLEEPVCC HOLD
PGOOD (Boost)GND (weak pull-down)GNDEnabled, monitors UVMonitors OV for bypass operation.OpenGND
PGOOD (Buck)GND (weak pull-down)GNDEnabled, monitors both UV and OVOpenOpenGND
FB (Boost)DisabledVOUT1 is adjustable.EnabledDisabled
FB (Buck)DisabledFB mode detectionEnabled if VOUT is adjustable. Open otherwise.Disabled
COMP (Boost)DischargedGNDEnabledGND
COMP (Buck)DischargedGNDEnabled. COMP3 = COMP2 if dual-phase buckGND
SS (Boost)DischargedGNDEnabledPullup to VDDPullup to VDDGND
SS (Buck)DischargedGNDEnabled. SS3 = SS2 if dual-phase buckPullup to VDDGND
HB-SW (Boost)DischargedCharge pump is onHB-SW ≈5 VHB-SW ≈5 V by charge pumpDischarging. Charge pump is off
HB-SW (Buck)DischargedCharged when VOUT<VCC HB-SW ≈5 VDischarging
HO-SW (Boost)Open2-kΩ pulldown resistorSwitchingPull up in bypass. Pull down otherwisePull up, but will be off when HB UVPull down
HO-SW (Buck)Open2-kΩ pulldown resistorSwitchingPull down
LO-PGND (Boost)OpenPull downSwitchingPull down
LO-PGND (Buck)OpenPull downSwitchingPull down