These items must be applied to every channel.

• Populate the device on the top layer.
• Connect the PGND1, PGND2, and PGND3 pins to the DAP directly on the top layer.
• Populate a common 10-μF VCC capacitor between VCC and DAP on the bottom layer.
• Use a differential mode filters (100 Ω and 220 pF) at CSA-CSB. Connect the 100 Ω to CSA.
• Route CSA and CSB traces in parallel.
• Populate 0.1-μF HB capacitors between HB and SW on the top layer.
• Connect the SENSE1 pin to the drain connection of the high-side MOSFET in boost.
• Connect the SENSE1 pin to the output in SEPIC topology.
• Connect a 1-μF BIAS capacitor between BIAS and ground.
• Connect a 0.1-μF VDD capacitor between VDD and AGND.
• Connect the loop compensation components between COMP to AGND.

These items must be applied to every buck channel.

• Populate 0.1-μF local VCC capacitors between VCC and PGND on the top layer.
• Populate local boot diodes (Schottky diode) from the positive connection of the local VCC capacitors to the positive connection of the HB capacitors on the top layer.
• Populate minimum 1.5-Ω gate resistors from HO to the gate of high-side MOSFET and populate pull-down PNP transistors in parallel.
• Populate minimum 1.5-Ω gate resistors from LO to the gate of low-side MOSFET and populate pull-down PNP transistors in parallel.
• Use the low-side MOSFET whose r_DS(on) is greater than 8 mΩ at the room temperature.
• Connect the source connection of the low-side MOSFET to PGND directly with minimum 2.5-mm width trace (length < 0.8 inch).
• Connect the drain connection of the low-side MOSFET to SW directly with minimum 2.5-mm width trace (length < 0.8 inch).
• Route SW and PGND in parallel.

These items must be applied when CH2 and CH3 are configured as a dual-phase interleaved buck.

• Place two R_S resistors as close as possible.
• Place a ceramic output capacitor from the midpoint between two resistors and output ground.