SLVSES8A October   2020  – December 2020 LM5127-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Enable (EN, VCC_HOLD)
      2. 8.3.2  Dual Input VCC Regulator (BIAS, VCCX, VCC)
      3. 8.3.3  Dual Input VDD Switch (VDD, VDDX)
      4. 8.3.4  Device Configuration and Light Load Switching Mode Selection (CFG/MODE)
      5. 8.3.5  Fixed or Adjustable Output Regulation Target (VOUT, FB)
      6. 8.3.6  Overvoltage Protection (VOUT, FB)
      7. 8.3.7  Power Good Indicator (PGOOD)
      8. 8.3.8  Programmable Switching Frequency (RT)
      9. 8.3.9  External Clock Synchronization (SYNC)
      10. 8.3.10 Programmable Spread Spectrum (DITHER)
      11. 8.3.11 Programmable Soft Start (SS)
      12. 8.3.12 Fast Re-start using VCC_HOLD (VCC_HOLD)
      13. 8.3.13 Transconductance Error Amplifier and PWM (COMP)
      14. 8.3.14 Current Sensing and Slope Compensation (CSA, CSB)
      15. 8.3.15 Constant Peak Current Limit (CSA, CSB)
      16. 8.3.16 Maximum Duty Cycle and Minimum Controllable On-time Limits (Boost)
      17. 8.3.17 Bypass Mode (Boost)
      18. 8.3.18 Minimum Controllable On-time and Minimum Controllable Off-time Limits (Buck)
      19. 8.3.19 Low Dropout Mode for Extended Minimum Input Voltage (Buck)
      20. 8.3.20 Programmable Hiccup Mode Overload Protection (RES)
      21. 8.3.21 MOSFET Drivers and Hiccup Mode Fault Protection (LO, HO, HB)
      22. 8.3.22 Battery Monitor (BMOUT, BMIN_FIX, BMIN_PRG)
      23. 8.3.23 Dual-phase Interleaved Configuration for High Current Supply (CFG)
      24. 8.3.24 Thermal Shutdown Protection
      25. 8.3.25 External VCCX Supply Reduces Power Dissipation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Status
        1. 8.4.1.1 Shutdown Mode
        2. 8.4.1.2 Configuration Mode
        3. 8.4.1.3 Active Mode
        4. 8.4.1.4 Sleep Mode
        5. 8.4.1.5 Deep Sleep Mode
          1. 8.4.1.5.1 Cutting Leakage Path in Deep Sleep Mode (DIS, SLEEP1, SENSE1)
        6. 8.4.1.6 VCC HOLD Mode
      2. 8.4.2 Light Load Switching Mode
        1. 8.4.2.1 Forced PWM (FPWM) Operation
        2. 8.4.2.2 Diode Emulation (DE) Operation (Connect RSS at SS)
        3. 8.4.2.3 Forced Diode Emulation Operation in FPWM Mode
        4. 8.4.2.4 Skip Mode Operation
      3. 8.4.3 LM5127 Cheat Sheet
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Recommended Power Tree Architecture
        2. 9.2.2.2 Application Ideas
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range(1)
MIN MAX UNIT
Input(4) BIAS, SENSE1 to AGND –0.3 50 V
DIS, FB1, SLEEP1 to AGND –0.3 SENSE1+0.3
ENx to AGND –0.3 BIAS+0.3
VCCX to AGND –0.3 5.8(2)
SWx to AGND (50ns) –1
HBx to AGND –0.3 50
HBx to SWx –0.3 5.8(2)
HB1 to BIAS 40
CSBx to AGND –0.3 50
CSAx to CSBx –0.3 0.3
CFG, FB2, FB3 to AGND –0.3 5.5
SYNC, RES, RT to AGND –0.3 VDD+0.3
PGNDx to AGND –0.3 0.3
Output(4) HOx to SWx (50ns) –1 V
LOx to PGND (50ns) –1
VCC, VDD to AGND –0.3 5.8(2)
PGOODx(5), SSx, COMPx to AGND –0.3 5.5
Junction temperature, TJ (3) –40 150 °C
Storage temperature, TSTG  –55 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Operating lifetime is de-rated when the pin voltage is greater than 5.5V.
(3) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
(4) It is not allowed to apply an external voltage to the COMPx, SSx, RT, CFG, LOx, HOx pins.
(5) The maximum current sink is limited to 1 mA when VPGOOD > VBIAS